Commit Graph

17 Commits

Author SHA1 Message Date
Florent Kermarrec 125432b5b6 liteeth/example_designs: use new Keep SynthesisDirective 2015-06-23 16:15:28 +02:00
Florent Kermarrec 369cf4c4d7 liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection 2015-06-23 01:08:49 +02:00
Florent Kermarrec a99aa9c7fd uart: rename wishbone to bridge 2015-05-09 16:24:28 +02:00
Florent Kermarrec fb5397aa82 uart: remove litescope dependency for UARTWishboneBridge and remove frontend 2015-05-09 16:08:20 +02:00
Florent Kermarrec 3ebe877fd2 use similar names for wishbone bridges and move wishbone drivers to [core]/software 2015-05-02 16:22:30 +02:00
Florent Kermarrec 1281a463d6 litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
Florent Kermarrec d253adee61 liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend 2015-04-28 18:51:40 +02:00
Florent Kermarrec 5720638d85 liteeth: pep8 (E302) 2015-04-13 10:20:02 +02:00
Florent Kermarrec cd43eaffc2 liteeth: pep8 (replace tabs with spaces) 2015-04-13 09:53:43 +02:00
Florent Kermarrec dcdf5df4de adapt LiteEth to new SoC 2015-04-01 22:50:29 +02:00
Florent Kermarrec 236ea0f572 liteeth: use bios ip_address in example designs 2015-03-18 18:18:43 +01:00
Florent Kermarrec ec6ae75065 liteeth: use CRG from Migen in base example 2015-03-17 12:11:51 +01:00
Florent Kermarrec 649cdeb265 liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen 2015-03-01 16:48:41 +01:00
Florent Kermarrec b32a0e6f9e liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins 2015-02-28 23:33:00 +01:00
Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
Florent Kermarrec c4ebf244a1 litescope: move files and modify import to misoclib.tools.litescope 2015-02-28 10:33:46 +01:00
Florent Kermarrec 2c51adcd68 misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00