518aaeaacb
Merge pull request #863 from Dolu1990/master
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cpu/vexriscv_smp add RVC support
2021-03-25 16:26:30 +01:00
4246f77a97
integration/soc/add_scard: Revert use of self.csr.add since to avoid breaking Linux driver that currently relies on implicit ordering (but probably shoudln't :)).
2021-03-25 14:54:34 +01:00
e755a02b84
cpu/vexriscv_smp add RVC support
2021-03-25 14:17:19 +01:00
aad56a047a
integration/soc: Use CSR automatic allocation.
2021-03-25 10:09:54 +01:00
aa9eb1f6a3
integration/soc: Add CSR automatic allocation and enable it by default.
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Un-allocated CSRs were already automatically detected so when un-allocated we can just
simply allocate them automatically instead of raising an error. This also allows
simplifying user's code since self.csr.add/self.add_csr will no longer be required.
2021-03-25 09:49:59 +01:00
3def6ae985
integration/soc: Be sure all add_xy methods use check_if_exists, improve Video integration.
2021-03-25 09:29:33 +01:00
c9ac5424f4
integration/soc: Cosmetic cleanup pass.
2021-03-25 09:13:43 +01:00
6e23fb1d99
integration/soc: Move Identifier import to add_identifier.
2021-03-25 08:47:05 +01:00
e1b20a934a
integation/soc: Move VideoXY imports to add_video_xy.
2021-03-25 08:45:55 +01:00
1b9eefbee4
integration/soc: Move Timer import to add_timer.
2021-03-25 08:43:52 +01:00
01fdca9149
integration/soc: Move SPIMaster import to add_spi_sdcard.
2021-03-25 08:42:23 +01:00
5229727c2b
integration/soc: Move SpiFlash import to add_spi_flash.
2021-03-25 08:40:53 +01:00
c60938d7aa
integration/soc/ethernet: Simplify timing constraints.
2021-03-25 08:36:37 +01:00
e27330b0d9
integration/soc: Replace self.add_csr with self.csr.add.
2021-03-25 08:23:39 +01:00
36bb069b8b
interconnect/packet: Minor cleanup.
2021-03-24 18:04:20 +01:00
6c640b0693
compat/stream_sim: Remove TODO since will not be done.
2021-03-24 17:58:13 +01:00
9eb318e86a
soc/interconnect/stream_sim: Move to compat to prevent since no longer really used or recommended on new designs.
2021-03-24 17:56:21 +01:00
bc8974dad1
litex_sim: Switch to soc_core_args/soc_core_argdict.
2021-03-24 17:26:48 +01:00
ee36138f75
compat: Fix (only triggers notice when used) and enable SoCSDRAM compat.
2021-03-24 17:21:26 +01:00
50ed5e262d
integration/soc_core: Move L2/SDRAM arguments soc_core_args.
2021-03-24 17:21:22 +01:00
ad63f8edc8
compat: Add Retro-Compat for litex.soc.cores.up5kspram (that has now moved to litex.soc.cores.ram).
2021-03-24 17:21:18 +01:00
f7f277548e
Compat: Add litex.compat to handle retro-compatibility on API changes and move integration/soc_sdram to it.
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Compat Notice is not yet enabled for soc_sdram since targets first need to be updated.
2021-03-24 17:21:13 +01:00
cc02055b42
Merge pull request #859 from Dolu1990/master
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soc/cores/cpu/vexriscv_smp cpu per fpu ratio
2021-03-24 08:03:38 +01:00
391a4429dc
soc/cores/cpu/vexriscv_smp add cpu_per_fpu option to change the ratio core count and FPU
2021-03-23 20:05:28 +01:00
9e341544d5
Merge pull request #858 from antmicro/jboc/gtkwave-fix
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gtkwave: fix error when prefix is empty, make treeopen optional
2021-03-23 17:02:23 +01:00
bea82efc5d
gtkwave: fix error when prefix is empty, make treeopen optional
2021-03-23 10:08:06 +01:00
9113c1a2f9
cores/gpio/GPIOIRQ: Add mode CSR (Edge or Change) and rename polarity CSR to edge.
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Allow interrupts on Change, Rising Edge or Falling Edge.
2021-03-20 21:49:12 +01:00
c2f65b2b04
Merge pull request #850 from Dolu1990/master
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cpu/vexriscv_smp add FPU support
2021-03-19 09:08:44 +01:00
db353526c1
Merge pull request #853 from mczerski/liteeth_slots
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liteeth: allow to specify nrxslots and ntxslots for liteeth
2021-03-19 08:58:44 +01:00
d0c4199096
cores/gpio: Fix GPIOIRQ.
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Compilation tested in Arty with:
from litex.soc.cores.gpio import GPIOIn
self.submodules.gpio_in = GPIOIn(platform.request("user_sw", 0), with_irq=True)
self.add_csr("gpio_in")
self.add_interrupt("gpio_in")
2021-03-18 19:05:12 +01:00
1bb4507d93
Merge pull request #846 from enjoy-digital/axi-lite-downconverter-fix
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interconnect/axi: Fix AXILiteDownverterWrite/Read base address.
2021-03-18 18:15:52 +01:00
8460523f27
cores/video: Add VideoECP5HDMI PHY and move 10to1 Serializer to Generic, share it for Spartan6/ECP5.
2021-03-18 14:43:21 +01:00
e5695f9934
cores/video: Add VideoS6HDMIPHY (using stream.Gearbox for 10:2 convertion).
2021-03-18 13:49:50 +01:00
c01284fa23
integration/soc/add_video_colorbars: Review/Fix #849 (Fix ColorBarsPattern clock domain).
2021-03-18 13:48:53 +01:00
675349055b
inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2.
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Allow supporting all cases.
2021-03-18 13:47:10 +01:00
6eaa426e37
liteeth: allow to specify nrxslots and ntxslots for liteeth
2021-03-18 09:24:48 +01:00
6b387eb579
cpu/vexriscv_smp add FPU support
2021-03-17 13:20:45 +01:00
a166a8dba3
Merge pull request #849 from hansfbaier/add-video-colorbars
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video: convenience method to add color bar pattern
2021-03-16 12:51:27 +01:00
c071bb4ac7
software/liblitesdcard: Check sdcard_wait_data_done in sdcard_switch/sdcard_app_send_scr since requesting a data read transfer.
2021-03-16 12:44:00 +01:00
f86c743c58
video: convenience method to add color bar pattern
2021-03-16 12:35:58 +07:00
04cb8e0e5e
cores/xadc: Review/Cleanup PR#838, rename _XADC to SystemMonitorDRP and USSYSMON to USSystemMonitor.
2021-03-15 10:35:10 +01:00
367b510590
Merge pull request #838 from jersey99/ussysmon
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Ussysmon: SYSMONE1 for US devices
2021-03-15 10:19:54 +01:00
13e13a094c
soc/interconnect/axi: Add AXILite Clock Domain Crossing module.
2021-03-15 10:18:12 +01:00
11f7416e36
Merge pull request #847 from zoobab/master
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Add support for xcompiler on Alpine 3.13
2021-03-12 21:49:44 +01:00
0456de50aa
Add support for xcompiler on Alpine 3.13
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Problem: xcompiler on Alpine 3.13 was not found
Solution is to add "riscv-none-elf-gcc":
1. Add Edge to your repositories:
$ echo -e "http://dl-cdn.alpinelinux.org/alpine/edge/main\nhttp://dl-cdn.alpinelinux.org/alpine/edge/testing\nhttp://dl-cdn.alpine
linux.org/alpine/edge/community" >> /etc/apk/repositories
$ apk update
$ apk add gcc-riscv-none-elf
2. The xcompiler should be found at:
$ which riscv-none-elf-gcc
/usr/bin/riscv-none-elf-gcc
2021-03-12 20:13:23 +01:00
1e9606f3fb
software/liblitedram: Improve find_cmd_delay to favor higher number of valid modules and centered scan.
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Also add an optional debug #define to look at cmd/clk centering scans:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Mar 12 2021 14:06:20
BIOS CRC passed (116682af)
Migen git sha1: 7014bdc
LiteX git sha1: edcc0f88
--=============== SoC ==================--
CPU: VexRiscv @ 125MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 1048576KiB 64-bit @ 1000MT/s (CL-7 CWL-6)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
tCK/4 taps: 6
Cmd/Clk scan (0-12)
|Cmd/Clk delay: 0
m0: |11000000000000011111111111| delay: 15
m1: |00000000000000111111111111| delay: 14
m2: |11110000000000000111111111| delay: 17
m3: |11110000000000000011111111| delay: 18
m4: |11111111110000000000000111| delay: -
m5: |11111111110000000000000111| delay: -
m6: |11111111111000000000000001| delay: -
m7: |11111111111000000000000011| delay: -
Delay mean: 22, ideal: 13
Cmd/Clk delay: 1
m0: |11100000000000001111111111| delay: 16
m1: |10000000000000011111111111| delay: 15
m2: |11111000000000000011111111| delay: 18
m3: |11111000000000000001111111| delay: 19
m4: |11111111111000000000000011| delay: -
m5: |11111111111000000000000011| delay: -
m6: |11111111111100000000000000| delay: -
m7: |11111111111100000000000001| delay: -
Delay mean: 23, ideal: 13
Cmd/Clk delay: 2
m0: |11110000000000000111111111| delay: 17
m1: |11000000000000001111111111| delay: 16
m2: |11111100000000000001111111| delay: -
m3: |11111100000000000000111111| delay: -
m4: |11111111111100000000000001| delay: -
m5: |11111111111100000000000001| delay: -
m6: |11111111111110000000000000| delay: -
m7: |11111111111110000000000000| delay: -
Delay mean: 22, ideal: 13
Cmd/Clk delay: 3
m0: |11111000000000000011111111| delay: 18
m1: |11100000000000000111111111| delay: 17
m2: |11111110000000000000111111| delay: -
m3: |11111110000000000000011111| delay: -
m4: |11111111111110000000000000| delay: -
m5: |11111111111110000000000000| delay: -
m6: |01111111111111000000000000| delay: 01
m7: |01111111111111000000000000| delay: 01
Delay mean: 15, ideal: 13
Cmd/Clk delay: 4
m0: |11111100000000000001111111| delay: -
m1: |11110000000000000011111111| delay: 18
m2: |11111111000000000000011111| delay: -
m3: |11111111000000000000001111| delay: -
m4: |11111111111111000000000000| delay: -
m5: |11111111111111000000000000| delay: -
m6: |00111111111111100000000000| delay: 02
m7: |00111111111111100000000000| delay: 02
Delay mean: 13, ideal: 13
Cmd/Clk delay: 5
m0: |11111110000000000000111111| delay: -
m1: |11111000000000000001111111| delay: 19
m2: |11111111100000000000001111| delay: -
m3: |11111111100000000000000111| delay: -
m4: |01111111111111100000000000| delay: 01
m5: |01111111111111100000000000| delay: 01
m6: |00011111111111110000000000| delay: 03
m7: |00011111111111110000000000| delay: 03
Delay mean: 11, ideal: 13
Cmd/Clk delay: 6
m0: |11111111000000000000011111| delay: -
m1: |11111100000000000000111111| delay: -
m2: |11111111110000000000000111| delay: -
m3: |11111111110000000000000011| delay: -
m4: |00111111111111110000000000| delay: 02
m5: |00011111111111110000000000| delay: 03
m6: |00001111111111111000000000| delay: 04
m7: |00001111111111111000000000| delay: 04
Delay mean: 9, ideal: 13
Cmd/Clk delay: 7
m0: |11111111100000000000001111| delay: -
m1: |11111110000000000000011111| delay: -
m2: |11111111111000000000000011| delay: -
m3: |11111111111000000000000001| delay: -
m4: |00011111111111111000000000| delay: 03
m5: |00001111111111111000000000| delay: 04
m6: |00000111111111111100000000| delay: 05
m7: |00000111111111111100000000| delay: 05
Delay mean: 10, ideal: 13
Cmd/Clk delay: 8
m0: |11111111110000000000000111| delay: -
m1: |11111111000000000000001111| delay: -
m2: |11111111111100000000000001| delay: -
m3: |11111111111100000000000000| delay: -
m4: |00001111111111111100000000| delay: 04
m5: |00000111111111111100000000| delay: 05
m6: |00000011111111111110000000| delay: 06
m7: |00000011111111111110000000| delay: 06
Delay mean: 11, ideal: 13
Cmd/Clk delay: 9
m0: |11111111111000000000000011| delay: -
m1: |11111111100000000000000111| delay: -
m2: |11111111111110000000000000| delay: -
m3: |11111111111110000000000000| delay: -
m4: |00000111111111111110000000| delay: 05
m5: |00000011111111111110000000| delay: 06
m6: |00000001111111111111000000| delay: 07
m7: |00000001111111111111000000| delay: 07
Delay mean: 12, ideal: 13
Cmd/Clk delay: 10
m0: |11111111111100000000000011| delay: -
m1: |11111111110000000000000011| delay: -
m2: |01111111111111000000000000| delay: 01
m3: |01111111111111000000000000| delay: 01
m4: |00000011111111111111000000| delay: 06
m5: |00000001111111111111000000| delay: 07
m6: |00000000111111111111100000| delay: 08
m7: |00000000111111111111100000| delay: 08
Delay mean: 11, ideal: 13
Cmd/Clk delay: 11
m0: |11111111111110000000000001| delay: -
m1: |11111111111000000000000001| delay: -
m2: |00111111111111100000000000| delay: 02
m3: |00111111111111100000000000| delay: 02
m4: |00000001111111111111100000| delay: 07
m5: |00000000111111111111100000| delay: 08
m6: |00000000011111111111110000| delay: 09
m7: |00000000011111111111110000| delay: 09
Delay mean: 12, ideal: 13
| best: 11
Setting Cmd/Clk delay to 11 taps.
Data scan:
m0: |11111111111110000000000001| delay: -
m1: |11111111111000000000000001| delay: -
m2: |00111111111111100000000000| delay: 02
m3: |00111111111111100000000000| delay: 02
m4: |00000001111111111111100000| delay: 07
m5: |00000000111111111111100000| delay: 08
m6: |00000000011111111111110000| delay: 09
m7: |00000000011111111111110000| delay: 09
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |11111111100000000000000000000000| delays: 04+-04
m0, b4: |00000000000001111111110000000000| delays: 17+-04
m0, b5: |00000000000000000000000000111111| delays: 29+-03
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b03 delays: 04+-04
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |11111111000000000000000000000000| delays: 04+-04
m1, b4: |00000000000011111111100000000000| delays: 16+-04
m1, b5: |00000000000000000000000000111111| delays: 29+-03
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b04 delays: 16+-04
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |11111110000000000000000000000000| delays: 03+-03
m2, b4: |00000000000111111111000000000000| delays: 15+-04
m2, b5: |00000000000000000000000011111111| delays: 28+-04
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b04 delays: 15+-04
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |11111110000000000000000000000000| delays: 03+-03
m3, b4: |00000000001111111110000000000000| delays: 14+-04
m3, b5: |00000000000000000000000011111111| delays: 28+-04
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b04 delays: 14+-04
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |10000000000000000000000000000000| delays: -
m4, b4: |00001111111110000000000000000000| delays: 08+-04
m4, b5: |00000000000000000111111111000000| delays: 22+-05
m4, b6: |00000000000000000000000000000001| delays: 31+-00
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b04 delays: 08+-04
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |00001111111110000000000000000000| delays: 08+-04
m5, b5: |00000000000000000011111111000000| delays: 22+-04
m5, b6: |00000000000000000000000000000001| delays: 31+-00
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b04 delays: 08+-04
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |00111111110000000000000000000000| delays: 06+-04
m6, b5: |00000000000000111111111000000000| delays: 18+-04
m6, b6: |00000000000000000000000000001111| delays: 30+-02
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b05 delays: 19+-04
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |01111111111100000000000000000000| delays: 06+-05
m7, b5: |00000000000000011111111110000000| delays: 20+-05
m7, b6: |00000000000000000000000000001111| delays: 30+-02
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b04 delays: 06+-05
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 40MiB/s
Read speed: 33MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
2021-03-12 14:34:49 +01:00
3cbdc567ff
soc: Add init_rom to initialize ROM and contents and with auto_size option (enable by default) to reduce ROM size to length of contents when in Read Only mode.
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This ensures the integrated ROM is reduced to minimal size before build and avoid having to adjust it manually with --integrated-rom-size on targets.
2021-03-12 09:42:59 +01:00
d9b6d7608c
soc/integration/soc_core: Cleanup SoCCore arguments.
2021-03-12 09:03:17 +01:00
21273ffe87
soc/integration/builder: Cleanup and add comments.
2021-03-11 16:21:45 +01:00
cba4642444
Merge pull request #845 from meklort/meklort/xics-fix
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xics: Disable endianness swapping
2021-03-11 13:33:15 +01:00
enjoy-digital
Dolu1990
Jędrzej Boczar
Marek Czerski
Hans Baier
Benjamin Henrion