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Author SHA1 Message Date
Tim 'mithro' Ansell
5a0bb6ee01 litex_sim: Rework Makefiles to put output files in gateware directory. 2020-04-11 18:37:03 -07:00
Tim 'mithro' Ansell
a0658421cc litex_sim: Better error messages on failure to load module. 2020-04-11 18:35:39 -07:00
Florent Kermarrec
d0d2f2824b README: LiteDRAM moved to travis-ci.com as others repositories. 2020-04-10 19:11:21 +02:00
Florent Kermarrec
b95e0a19b1 altera/common: add DDROutput, DDRInput, SDROutput, SDRInput. 2020-04-10 15:50:35 +02:00
Florent Kermarrec
40f43efcf6 targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets. 2020-04-10 14:41:01 +02:00
Florent Kermarrec
292d6b75b6 build/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTristate. 2020-04-10 14:38:22 +02:00
Florent Kermarrec
88dc5158c1 build/io: add SDR Tristate (with infered version) and remove multi-bits support on SDRIO. 2020-04-10 14:37:29 +02:00
Florent Kermarrec
fdadbd868b build/lattice/common: remove multi-bits support on SDRInput/Output. 2020-04-10 14:36:13 +02:00
Florent Kermarrec
8159b65bee litex/build/io: also import CRG (since using DifferentialInput). 2020-04-10 10:25:21 +02:00
Florent Kermarrec
79913e8614 litex.build: update from migen.genlib.io litex.build.io. 2020-04-10 09:49:45 +02:00
Florent Kermarrec
8e014f76da litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen. 
This will make things easier and more consistent, all special IO primitives are now in LiteX.
 2020-04-10 08:47:07 +02:00
Florent Kermarrec
2e270cf28c platforms/versa_ecp5: remove Lattice Programmer (no longer used since we can now use OpenOCD). 2020-04-09 23:08:59 +02:00
Florent Kermarrec
deebc49ab0 boards/platforms: cosmetic cleanups. 2020-04-09 23:04:29 +02:00
Florent Kermarrec
3c0ba8ae62 boards/plarforms/ulx3s: cleanup, fix user_leds, add spisdcard, add PULLMODE/DRIVE on SDRAM pins. 2020-04-09 18:55:01 +02:00
Florent Kermarrec
6c429c9995 build/lattice: add ECP5 implementation for SDRInput/SDROutput. 2020-04-09 16:24:05 +02:00
Florent Kermarrec
72c8d590fa litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered). 2020-04-09 16:23:27 +02:00
Florent Kermarrec
8f57321f30 tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others sub-projects. 
LiteSPI is not mature enough to be integrated in LiteX sim directly. (will case trouble is things are refactored).

This could be re-introduced later when more mature. For now simulation with LiteX Sim
could be tested directly in LiteSPI with a custom simulation.
 2020-04-09 11:14:19 +02:00
Florent Kermarrec
9afd017a3a tools/litex_term: increase workaround delay for usb_fifo. (validated on Minispartan6 and MimasA7). 
Still needs to be fixed properly.
 2020-04-09 10:52:15 +02:00
enjoy-digital
fdfede2281
Merge pull request #459 from mithro/travis-fix 
Two small Travis-CI related patches
 2020-04-09 09:01:59 +02:00
Tim 'mithro' Ansell
cb7e309966 travis: Run Windows build but allow it to fail. 2020-04-08 23:14:55 -07:00
Tim 'mithro' Ansell
43242012ea travis: Use litex_setup.py from the checked out code. 2020-04-08 23:14:55 -07:00
Tim Ansell
30f5faf9bc
Merge pull request #458 from david-sawatzke/add_triple 
Add riscv64-none-elf triple
 2020-04-08 21:39:29 -07:00
David Sawatzke
d69b4443b3 Add riscv64-none-elf triple 2020-04-09 05:36:10 +02:00
Florent Kermarrec
14bf8b8190 soc/cores/clock: add Max10PLL. 2020-04-08 08:54:12 +02:00
Florent Kermarrec
2470ef5096 soc/cores/clock: add Cyclone10LPPLL. 2020-04-08 08:33:57 +02:00
Florent Kermarrec
f8d6d0fda8 soc/cores/clock/CycloneVPLL: fix typos. 2020-04-08 08:25:46 +02:00
Florent Kermarrec
970c8de4c2 soc/cores/clock: rename Altera to Intel. 2020-04-08 08:16:37 +02:00
Florent Kermarrec
383fcd36d6 soc/cores/clock: add CycloneVPLL. 2020-04-07 17:24:12 +02:00
Florent Kermarrec
ab4906ea3b targets/de0nano: use CycloneIVPLL, remove 50MHz limitation. 2020-04-07 17:00:45 +02:00
Florent Kermarrec
0f17547c5b soc/cores/clock: add initial AlteraClocking/CycloneIV support. 2020-04-07 16:59:53 +02:00
Florent Kermarrec
3575d03faa .travis.yml: disable windows test (failing for now). 2020-04-07 12:43:29 +02:00
Florent Kermarrec
2ca853fd74 README.md: update RISCV toolchain installation. 2020-04-07 12:39:52 +02:00
Florent Kermarrec
d770bfbf2e .travis.yml: remove Python3.5 test. 2020-04-07 12:33:56 +02:00
enjoy-digital
bc26af0d47
Merge pull request #451 from mithro/multi-os 
Add multiple Python versions, Windows and Mac to Travis CI testing
 2020-04-07 12:29:04 +02:00
Florent Kermarrec
30d25ffe5b setup.py: simplify, switch to Python3.6+ (using python_requires), remove version. 
- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
 2020-04-07 11:48:16 +02:00
Florent Kermarrec
3f1159fa0b litex_setup: reorganize a bit, add separators/comments. 2020-04-07 11:05:36 +02:00
Florent Kermarrec
926f961bf3 .travis.yml: revert full url for litex_setup.py. 
We want to have an almost identical .travis.yml between LiteX and the Cores.
Using $TRAVIS_BUILD_DIR works for LiteX but will not work for the cores.
 2020-04-07 10:55:58 +02:00
enjoy-digital
447e8d948c
Merge pull request #452 from mithro/riscv-download 
Add GCC downloading via litex_setup.py
 2020-04-07 10:51:27 +02:00
Tim 'mithro' Ansell
3305a65b77 Enable testing on multiple Python versions. 
Makes sure LiteX tests pass on all supported Python versions.
 2020-04-06 17:58:12 -07:00
Tim 'mithro' Ansell
6bd5eae43f Enable CI for Windows and Mac. 2020-04-06 17:58:12 -07:00
Tim 'mithro' Ansell
9e324d9e16 Remove symlinking step. 2020-04-06 17:57:32 -07:00
Tim 'mithro' Ansell
7f0ecddfb2 Use shutil.unpack_archive. 2020-04-06 17:45:55 -07:00
Tim 'mithro' Ansell
a1dd8fc883 Ignore SSL errors on CI. 2020-04-06 17:36:09 -07:00
Tim 'mithro' Ansell
2b2aff1274 Improve the path messages a little. 2020-04-06 17:27:24 -07:00
Tim 'mithro' Ansell
141644d157 Make travis use litex_setup.py for GCC download. 2020-04-06 17:16:55 -07:00
Tim 'mithro' Ansell
6adabae730 Adding SiFive RISC-V toolchain downloading to litex_setup.py 2020-04-06 16:51:14 -07:00
Tim 'mithro' Ansell
59b7db63b1 Fix alignments. 2020-04-06 16:51:14 -07:00
enjoy-digital
e408fb8f08
Merge pull request #450 from mithro/litex-setup-fix 
litex_setup: Use subprocess so failures are noticed.
 2020-04-06 23:04:47 +02:00
Tim 'mithro' Ansell
d781bf2088 Run litex_setup.py outside the git clone directory. 
Otherwise it tries to overwrite the litex directory by cloning LiteX
into it.
 2020-04-06 11:38:23 -07:00
Tim 'mithro' Ansell
dd59dac571 litex_setup: Use subprocess so failures are noticed. 
os.system doesn't report if any of the commands fail. This means that if
something goes wrong it happily reports success making it hard to debug
issues.
 2020-04-06 11:27:40 -07:00