Florent Kermarrec
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08935dce9a
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make.py: add powered by Migen
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2015-02-18 16:39:18 +01:00 |
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Florent Kermarrec
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e17791a85b
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readme/make.py: add powered by Migen
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2015-02-18 16:38:48 +01:00 |
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Florent Kermarrec
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2f6465d439
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add sigrok import (to check export against it)
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2015-02-18 15:23:04 +01:00 |
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Florent Kermarrec
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130212039e
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continue sigrok export (should almost work)
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2015-02-18 11:59:35 +01:00 |
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Florent Kermarrec
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cd43163d9d
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add sigrok export skeleton (wip)
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2015-02-18 00:44:33 +01:00 |
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Florent Kermarrec
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70f94ea0eb
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logo : add powered by Migen
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2015-02-17 23:17:46 +01:00 |
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Florent Kermarrec
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89eaef0e43
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logo : add powered by Migen
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2015-02-17 23:16:06 +01:00 |
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Florent Kermarrec
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5830575797
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logo : add powered by Migen
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2015-02-17 23:14:21 +01:00 |
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Florent Kermarrec
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79a7f9ecb8
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create BaseSoC as a basic example design and build UDPSoC/EtherboneSoC on top of it
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2015-02-17 12:37:17 +01:00 |
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Florent Kermarrec
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eeaf03669a
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test: we can now test regs with Etherbone
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2015-02-17 01:15:06 +01:00 |
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Florent Kermarrec
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a5416fa864
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host: add Etherbone driver
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2015-02-17 01:09:53 +01:00 |
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Florent Kermarrec
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1a3183c15d
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etherbone: fix addressing
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2015-02-17 00:02:49 +01:00 |
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Florent Kermarrec
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67958f7448
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mac: fix missing core csr generation
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2015-02-16 14:44:36 +01:00 |
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Florent Kermarrec
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da13bd536e
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gensoc: add csr_data_width and csr_address_width as parameters In some case we want to have mode than 32 CSR or and csr_data_width != 8
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2015-02-14 03:24:23 -08:00 |
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Florent Kermarrec
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3559de9b4c
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add setup.py
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2015-02-14 02:44:39 -08:00 |
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Florent Kermarrec
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d3cf2594f2
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update download instructions
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2015-02-12 22:03:24 +01:00 |
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Florent Kermarrec
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b64dba7a81
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update download instructions
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2015-02-12 22:03:04 +01:00 |
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Florent Kermarrec
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aedc964908
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update download instructions
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2015-02-12 22:02:50 +01:00 |
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Florent Kermarrec
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04f7fbd7e2
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simplify litescope export with do_exit call and remove automatic clean
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2015-02-12 21:15:51 +01:00 |
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Florent Kermarrec
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f8003c92aa
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simplify litescope export with do_exit call and remove automatic clean
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2015-02-12 21:04:52 +01:00 |
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Florent Kermarrec
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4e4800e1b2
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simplify litescope export with do_exit call
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2015-02-12 21:00:45 +01:00 |
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Florent Kermarrec
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61d12a3431
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fix transport_rx_description (detected with new Migen check)
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2015-02-12 20:45:15 +01:00 |
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Florent Kermarrec
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bceee36ef6
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etherbone: reads OK on hardware
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2015-02-12 15:50:07 +01:00 |
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Florent Kermarrec
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23c4f5c090
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etherbone: writes OK on hardware
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2015-02-12 13:15:30 +01:00 |
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Florent Kermarrec
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bfb50e698f
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etherbone: add more debug signals
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2015-02-12 12:33:10 +01:00 |
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Florent Kermarrec
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0818c29287
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etherbone: probing OK on hardware
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2015-02-12 12:17:17 +01:00 |
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Florent Kermarrec
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b6aeea676b
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etherbone: simplify model usage
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2015-02-12 12:09:39 +01:00 |
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Florent Kermarrec
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a2455b19af
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etherbone: create example design target
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2015-02-12 11:37:54 +01:00 |
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Florent Kermarrec
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f03212a30d
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cosmetic: define params before payload
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2015-02-12 11:10:05 +01:00 |
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Florent Kermarrec
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9eb2e313e7
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etherbone_tb: add autocheck
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2015-02-12 02:00:26 +01:00 |
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Florent Kermarrec
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d5887416f1
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code cleanup
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2015-02-12 01:30:17 +01:00 |
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Florent Kermarrec
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b8f2fc2290
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move generic modules to generic/__init__.py
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2015-02-12 01:19:36 +01:00 |
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Florent Kermarrec
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e4958ffab3
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etherbone: cleanup
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2015-02-12 01:12:52 +01:00 |
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Florent Kermarrec
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ea47037570
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etherbone_tb OK (will need cleanup)
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2015-02-12 00:01:03 +01:00 |
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Florent Kermarrec
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fca89e8b74
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etherbone: wishbone reads seems OK in simulation
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2015-02-11 21:51:25 +01:00 |
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Florent Kermarrec
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4a4e82b5f6
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etherbone: wishbone writes seems OK in simulation
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2015-02-11 20:54:32 +01:00 |
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Florent Kermarrec
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eee07e6eec
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etherbone: code wishbone master
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2015-02-11 19:44:02 +01:00 |
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Florent Kermarrec
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384fc3c868
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etherbone: record wip
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2015-02-11 18:37:59 +01:00 |
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Florent Kermarrec
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abe6d87438
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etherbone: add record depacketizer/packetizer (wip)
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2015-02-11 16:21:06 +01:00 |
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Florent Kermarrec
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247c30ae26
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etherbone: add etherbone_tb, able to probe etherbone endpoint
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2015-02-11 14:33:17 +01:00 |
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Florent Kermarrec
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a2279bd2fa
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models: use .format everywhere
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2015-02-11 11:28:15 +01:00 |
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Florent Kermarrec
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227fc4f5e5
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etherbone: cleanup model
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2015-02-11 11:11:54 +01:00 |
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Florent Kermarrec
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02bfc0a5a8
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etherbone: clean up ohwr dissector, Python model checked against it
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2015-02-10 23:05:36 +01:00 |
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Florent Kermarrec
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5728f61f3a
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etherbone: add model skeleton
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2015-02-10 22:45:10 +01:00 |
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Florent Kermarrec
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1de3bccfc8
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etherbone: add dissector from ohwr.org
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2015-02-10 18:43:14 +01:00 |
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Florent Kermarrec
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31bdc48a57
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etherbone: wip
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2015-02-10 16:43:31 +01:00 |
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Florent Kermarrec
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310040b43b
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test_udp: test loopback on port 6000 (dw=8) and port 8000 (dw=32) OK on board!
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2015-02-10 16:30:34 +01:00 |
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Florent Kermarrec
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974169218f
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targets/udp: create udp loopback on port 8000 with dw=32 (to test data_width converters)
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2015-02-10 16:24:45 +01:00 |
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Florent Kermarrec
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92904330f7
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phy: add hw_init_reset (useful when used without CPU)
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2015-02-10 16:03:07 +01:00 |
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Florent Kermarrec
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000ba7f0ab
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create Port class and remove connect method of mac/ip/udp Ports
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2015-02-10 15:37:29 +01:00 |