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5517 Commits

Author SHA1 Message Date
sadullah 5e4a436089 Vivado Command Update for Systemverilog 
Add BlackParrot to LiteX setup file
 2020-05-12 03:05:41 -04:00
enjoy-digital 3ce9010083
Merge pull request #505 from DurandA/patch-3 
Enable 1x mode on SPI flash
 2020-05-11 22:53:31 +02:00
Florent Kermarrec e2176cefc2 soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters. 2020-05-11 22:39:17 +02:00
Arnaud Durand 2c40967b5a Enable 1x mode on SPI flash 2020-05-11 22:12:40 +02:00
Florent Kermarrec 1e610600f6 build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends. 2020-05-11 10:52:39 +02:00
enjoy-digital ebcf67c10f
Merge pull request #502 from shuffle2/master 
diamond: project generation improvements
 2020-05-11 09:55:52 +02:00
enjoy-digital 80f5327e3d
Merge pull request #490 from daveshah1/rdimm_bside_init 
Add RDIMM side-B inversion support
 2020-05-11 09:42:55 +02:00
enjoy-digital 13db89ebd2
Merge branch 'master' into rdimm_bside_init 2020-05-11 09:42:35 +02:00
Florent Kermarrec c9e36d7fdd lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args. 2020-05-11 09:33:26 +02:00
Florent Kermarrec ea7fe383a3 lattice/trellis: simplify seed support and add it to trellis_args. 2020-05-11 09:26:12 +02:00
enjoy-digital 5ee01c9460
Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed 
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
 2020-05-11 09:13:26 +02:00
enjoy-digital 5987ddb454
Merge pull request #485 from ilya-epifanov/cpu-imac-config-for-vexriscv 
Added `imac` config for CPUs …
 2020-05-11 08:58:28 +02:00
enjoy-digital c5f74a5aa7
Merge branch 'master' into cpu-imac-config-for-vexriscv 2020-05-11 08:58:20 +02:00
Florent Kermarrec 59d88a880c integration/soc/add_adapter: rename is_master to direction. 2020-05-11 08:47:50 +02:00
enjoy-digital 57390666d8
Merge pull request #504 from sergachev/master 
integration/soc: fix add_adapter for slaves
 2020-05-11 08:34:03 +02:00
Ilia Sergachev e4fa4bbcf7 integration/soc: fix add_adapter for slaves 2020-05-10 11:32:34 +02:00
Benjamin Herrenschmidt 2d70220b80 bios: Fix warning on 64-bit 
This fixes an incorrect printf format specifier

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-09 19:44:43 +02:00
Shawn Hoffman eeee179dd8 diamond: close project when done 
Avoids ".recovery file is present" prompt.
 2020-05-09 02:28:00 -07:00
Shawn Hoffman 9b782bd7da diamond: clock constraint improvements 
Specify NET or PORT for freq constraints

Add equivalent timing closure check that diamond ui uses,
and default to asserting check has passed
 2020-05-09 02:28:00 -07:00
Florent Kermarrec fbbbdf03b5 core/led: simplify LedChaser (to have the same user interface than GPIOOut). 2020-05-08 22:13:47 +02:00
Florent Kermarrec 05869beb72 cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :)) 2020-05-08 13:18:12 +02:00
Florent Kermarrec 90c485fcc8 integration/soc: add clock_domain parameter to add_etherbone. 
To allow using a sys_clk < 125MHz with a 1Gbps link.
 2020-05-08 13:16:26 +02:00
Florent Kermarrec f1a50a2138 integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge). 2020-05-08 11:54:51 +02:00
Florent Kermarrec 79ee135f56 bios/sdram: fix lfsr typo. 2020-05-07 12:11:59 +02:00
enjoy-digital 162d32603d
Merge pull request #500 from mubes/fixups 
Fixups
 2020-05-07 11:55:58 +02:00
Florent Kermarrec d74f8fc93d build/xilinx: add disable_constraints parameter to Platform.add_ip. 
When integrate .xci, we don't necessarily want to apply the default timing/loc
constrants generated by Vivado but our custom ones. Setting disable_constraints
to True allow disabling .xdc generated by the IP.
 2020-05-07 11:34:26 +02:00
Dave Marples 2a37b97d9f Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups 2020-05-07 09:36:41 +01:00
Dave Marples 967e38bb57 Small fixups to address compiler warnings etc. 2020-05-07 09:26:46 +01:00
Florent Kermarrec 84841e1d58 bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt). 2020-05-07 08:21:57 +02:00
Benjamin Herrenschmidt 99c5b0fca1 bios/sdram: Use an LFSR to speed up pseudo-random number generation 
This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.

The LFSR implementation comes from microwatt's simple_random test
project.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-06 21:56:10 +02:00
enjoy-digital 34f268689a
Merge pull request #499 from DurandA/patch-2 
Add data dirs to manifest
 2020-05-06 18:54:23 +02:00
Florent Kermarrec 8b9aa16d2e boards/platforms: update xilinx programmers. 2020-05-06 16:16:41 +02:00
Florent Kermarrec 3c34039b73 build/xilinx/vivado: ensure Vivado process our .xdc early. 
When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.

Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.
 2020-05-06 13:13:01 +02:00
Arnaud Durand 5e049d8966 Add data dirs to manifest 2020-05-05 22:15:24 +02:00
Florent Kermarrec b057858071 gen/fhdl/verilog: explicitly define input/output/inout wires. 
When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
 2020-05-05 16:58:33 +02:00
Florent Kermarrec 0aa3c339cc targets/genesys2: set cmd_latency to 1. 2020-05-05 16:33:14 +02:00
Florent Kermarrec 95b57899cd bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases). 2020-05-05 16:27:21 +02:00
Florent Kermarrec 98d1b45157 platforms/targets: fix CI. 2020-05-05 15:55:09 +02:00
Florent Kermarrec 22bcbec03a boards: keep in sync with LiteX-Boards, integrate improvements. 
- create_programmer on all platforms.
- input clocks automatically constrainted.
- build/load parameters.
 2020-05-05 15:27:56 +02:00
Florent Kermarrec 28f85c7403 build/lattice/programmer: add UJProg (for ULX3S). 2020-05-05 13:31:58 +02:00
Florent Kermarrec 85ac5ef133 build/lattice/programmer: make OpenOCDJTAGProgrammer closer to OpenOCD programmer. 2020-05-05 12:17:12 +02:00
Florent Kermarrec 9a7f9cb87b build/generic_programmer: catch 404 not found when downloading config/proxy. 2020-05-05 12:16:29 +02:00
Florent Kermarrec d0b8daa005 build/platform: allow doing a loose lookup_request (return None instead of ConstraintError) and allow subname in lookup_request. 
In the platforms, insead of doing:
self.lookup_request("eth_clocks").rx
we can now do:
self.lookup_request("eth_clocks:rx")

This allows some try/except simplifications on constraints.
 2020-05-05 11:23:46 +02:00
Florent Kermarrec b8f9f83a8f build/openocd: add find_config method to allow using local config file or download it if not available locally. 2020-05-05 09:56:13 +02:00
Florent Kermarrec 9bef218ad6 cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt). 
Tested on Arty A7:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on May  4 2020 17:15:13
 BIOS CRC passed (0adc4193)

 Migen git sha1: 5b5e4fd
 LiteX git sha1: 6f24d46d

--=============== SoC ==================--
CPU:       Microwatt @ 100MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  262144KB

--========== Initialization ============--
Initializing SDRAM...
SDRAM now under software control
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000111111111111100000000000000| delays: 11+-06
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b6 delays: 11+-06
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |10000000000000000000000000000000| delays: 00+-00
m1, b6: |00000011111111111100000000000000| delays: 12+-06
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b6 delays: 12+-06
SDRAM now under hardware control
Memtest OK
Memspeed Writes: 129Mbps Reads: 215Mbps

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2020-05-04 17:30:50 +02:00
enjoy-digital 6f24d46dbd
Merge pull request #496 from gsomlo/gls-fix-makefiles 
software/*/Makefile: no need to copy .S files from CPU directory
 2020-05-04 15:29:05 +02:00
Gabriel Somlo edfed4f068 software/*/Makefile: no need to copy .S files from CPU directory 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-05-04 09:16:52 -04:00
enjoy-digital 7f8e34c65d
Merge pull request #494 from shuffle2/patch-2 
diamond: quiet warning about missing clkin freq for EHXPLLL
 2020-05-04 11:53:10 +02:00
shuffle2 ee413527ac
diamond: quiet warning about missing clkin freq for EHXPLLL 
FREQUENCY_PIN_CLKI should be given in mhz
 2020-05-04 01:10:09 -07:00
Florent Kermarrec 07e0153bb1 CHANGES: update. 2020-05-04 09:59:01 +02:00