Sebastien Bourdeauducq
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5405a83ff9
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fhdl: memories working
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2012-01-27 20:22:17 +01:00 |
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Sebastien Bourdeauducq
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a5bd111370
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fhdl/verilog: clean up signal classification and support memory descriptions
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2012-01-27 16:54:48 +01:00 |
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Sebastien Bourdeauducq
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d3d5b481fe
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Include fragment pads in pre-naming dictionary
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2012-01-20 22:59:40 +01:00 |
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Sebastien Bourdeauducq
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e9be3241f6
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Fix instance support
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2012-01-20 22:36:17 +01:00 |
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Sebastien Bourdeauducq
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e4f531a739
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Include unused I/Os in pre-naming dictionary and register signals with name_override
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2012-01-20 22:20:32 +01:00 |
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Sebastien Bourdeauducq
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4eac60d181
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New naming system: second attempt
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2012-01-19 18:25:25 +01:00 |
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Sebastien Bourdeauducq
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bdde97f5fd
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New naming system beginning to work
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2012-01-16 18:42:55 +01:00 |
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Sebastien Bourdeauducq
|
ab8e08a2ed
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fhdl: new naming system (broken)
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2012-01-16 18:09:52 +01:00 |
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Sebastien Bourdeauducq
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aa8b8da684
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fhdl: allow None statements
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2012-01-15 17:45:54 +01:00 |
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Sebastien Bourdeauducq
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7b395b565e
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verilog: split comb block, use assign statements
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2012-01-07 12:19:06 +01:00 |
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Sebastien Bourdeauducq
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f209bf6b33
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convtools -> tools
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2012-01-07 00:39:28 +01:00 |
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Sebastien Bourdeauducq
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9366a226bb
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Convert -> convert
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2012-01-05 19:27:33 +01:00 |
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Sebastien Bourdeauducq
|
8a394f9159
|
verilog: comb reset
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2011-12-22 00:04:53 +01:00 |
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Sebastien Bourdeauducq
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4d6be55e9f
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verilog: break down Convert function
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2011-12-21 23:08:50 +01:00 |
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Sebastien Bourdeauducq
|
26e0b817e8
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verilog: ignore variable property in combinatorial block
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2011-12-21 23:00:36 +01:00 |
|
Sebastien Bourdeauducq
|
7456195775
|
Consistent names
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2011-12-21 22:57:07 +01:00 |
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Sebastien Bourdeauducq
|
6f8a6db40a
|
verilog: get the simulator to run the combinatorial process at the beginning
|
2011-12-17 15:20:22 +01:00 |
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Sebastien Bourdeauducq
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ec47394012
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verilog: support for float parameters in instances
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2011-12-17 14:59:27 +01:00 |
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Sebastien Bourdeauducq
|
ee6ca729a2
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verilog: user-definable reset and clock
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2011-12-16 22:25:05 +01:00 |
|
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
|
c840848dba
|
verilog: use blocking assignment in combinatorial process
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2011-12-13 14:09:12 +01:00 |
|
Sebastien Bourdeauducq
|
a72faaecdd
|
fhdl: allow a namespace to be specified for Verilog conversion
|
2011-12-13 00:24:40 +01:00 |
|
Sebastien Bourdeauducq
|
eee6980a36
|
fhdl: support Constant parameters for Verilog conversion
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2011-12-11 20:17:51 +01:00 |
|
Sebastien Bourdeauducq
|
a49ecc4331
|
fhdl: pad support in fragments
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2011-12-10 20:25:24 +01:00 |
|
Sebastien Bourdeauducq
|
fa63cc1ec8
|
fhdl: replication support
|
2011-12-09 13:11:34 +01:00 |
|
Sebastien Bourdeauducq
|
b0c5b74c22
|
verilog: handle default in case statements
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2011-12-08 23:04:20 +01:00 |
|
Sebastien Bourdeauducq
|
bf021efa2b
|
verilog: fix unary operator conversion
|
2011-12-08 21:15:24 +01:00 |
|
Sebastien Bourdeauducq
|
1b637cea61
|
Instance support
|
2011-12-08 16:35:32 +01:00 |
|
Sebastien Bourdeauducq
|
0e8d894a35
|
Variable conversion
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2011-12-05 22:00:06 +01:00 |
|
Sebastien Bourdeauducq
|
4340680704
|
Cleanup
|
2011-12-05 19:25:32 +01:00 |
|
Sebastien Bourdeauducq
|
ec51f09c98
|
Case support + register bank generator
|
2011-12-05 17:43:56 +01:00 |
|
Sebastien Bourdeauducq
|
e099f4d52f
|
Reset insertion
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2011-12-04 22:41:50 +01:00 |
|
Sebastien Bourdeauducq
|
cd8544c758
|
Verilog generator
|
2011-12-04 22:26:32 +01:00 |