5f463dba87
CHANGES.md: Update.
2024-10-17 17:45:50 +02:00
aab8912f5a
soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU.
2024-10-17 17:44:40 +02:00
9449d25911
soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to synchronous memory.
...
- Replace im bus wishbone adaptation with synchronous memory (for now and initial tests).
- Correctly handle dm bus wishbone adaptation (Added FIFO).
2024-10-17 16:54:20 +02:00
edb56e73aa
soc/cores/cpu: Add initial uRV CPU support (not yet working).
2024-10-16 22:24:07 +02:00
c82fddf635
CHANGES.md: Update.
2024-10-15 12:54:37 +02:00
d5e4f9e975
soc/core/vexiiriscv : bring back xilinx support
2024-10-15 09:36:32 +02:00
7f04cafe08
soc/cores/cpu/zynqmp/core.py: add_ethernet: added gt_location required by SGMII
2024-10-10 17:28:29 +02:00
2935b7afb1
soc/cores/cpu/zynqmp/core.py: added missing pps signals
2024-10-10 17:26:35 +02:00
dc3364a3c7
CHANGES.md: Update.
2024-10-09 16:42:05 +02:00
01c7a78f67
Merge pull request #2095 from trabucayre/zynqmp_ethernet_sgmii
...
soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with optional PTP support
2024-10-09 16:38:33 +02:00
ddb8d16381
soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with option PTP support
2024-10-09 16:14:31 +02:00
34b98ab578
Merge pull request #2093 from mgaggero/feature-alpine-linux
...
Fixes #2092 : provides support for riscv gcc installation on Alpine Linux.
2024-10-09 06:32:05 +02:00
e148650279
Fixes #2092 : provides support for riscv gcc installation on Alpine
...
Linux.
2024-10-08 20:46:38 +02:00
bc3e90c93a
Merge pull request #2090 from VOGL-electronic/efinix_iobank
...
build: efinix: use ifacewriter to set bank voltage
2024-10-08 09:54:20 +02:00
d26994916d
build: efinix: use ifacewriter to set bank voltage
...
use efinix python api to set bank voltage,
instead of editing the peri.xml file.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-08 09:05:04 +02:00
9ad5d21231
Merge pull request #2089 from VOGL-electronic/efinix_tristate_fix
...
build: efinix: Tristate fix
2024-10-07 11:06:26 +02:00
4fcae9f3c7
build: efinix: Tristate fix
...
fix efinix Tristate by adding size to add_iface_io().
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-07 10:15:38 +02:00
64cf925b39
soc/integration/soc: Cleanup imports and directly use math.log2/ceil since math is already imported.
2024-10-02 17:10:08 +02:00
5e897752b7
soc/intergration/soc/add_pcie: Add new status_width parameter.
2024-10-02 17:10:05 +02:00
644ef7e4e5
Merge pull request #2086 from VOGL-electronic/build_io_clocksignal
...
build: io: don't use mutable object as default value
2024-10-01 11:49:03 +02:00
280b6b4ee4
build: io: don't use mutable object as default value
...
don't use mutable object (here: ClockSignal()) as default value,
beacuse they will be the same object.
Leeds to problems, when for example two `SDRInput`
are used in two different Modules and one of them is
used with a `ClockDomainsRenamer()`, then both are changed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-30 15:18:11 +02:00
87ee6ec3a0
CHANGES.md: Prepare for post 2024.08 changes.
2024-09-27 09:58:09 +02:00
f72368abaa
CHANGES.md: Do 2024.08 release.
2024-09-27 09:45:11 +02:00
58e916d86e
setup.py: 2024.08 release.
2024-09-27 09:37:11 +02:00
50bb6bb1ff
CHANGES.md: Update.
2024-09-27 09:33:22 +02:00
2130ff2fb3
build/efinix/efinity: Cosmetic cleanup on toolchain arguments.
2024-09-26 18:06:36 +02:00
1568b25ff7
build/efinix/common: Cosmetic cleanups.
2024-09-26 18:03:36 +02:00
431feb0ac2
build/efinix/common: Enable back SDRInput since support fixed with recent changes.
2024-09-26 18:01:02 +02:00
9760493c32
build/efinix/common: Switch to LiteXModule.
2024-09-26 17:46:07 +02:00
95e5e7302e
Merge pull request #2083 from VOGL-electronic/efinix_common_improve
...
build: efinix: EfinixTristateImpl: use GPIO Bus
2024-09-26 17:41:07 +02:00
c67dfa82cc
Merge pull request #2079 from VOGL-electronic/efinix_iface_fixups
...
build: efinix: ifacewriter: some fixes
2024-09-26 17:31:53 +02:00
a825c61385
build: efinix: EfinixTristateImpl: use GPIO Bus
...
use the gpio bus for Efinix Tristate implemenation.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:56 +02:00
e9a4b178ce
build: efinix: platform.py: add `get_pins_location` and `get_pins_name`
...
add `get_pins_location` and `get_pins_name`.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:56 +02:00
f8dc03810d
build: efinix: use LiteXContext to get platform
...
use LiteXContext to get platform.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:41 +02:00
afcc477c4e
efinix: common: replace `is_inclk_inverted`
...
replace `is_inclk_inverted` with `in_clk_inv` and `out_clk_inv`.
This way thwe right prop is set in the ifacewriter.py.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:11:39 +02:00
a605e75873
efinix: ifacewriter: remove deprecated GPIO properties
...
removes `OE_CLK_PIN_INV` and `OE_CLK_PIN` as they
got deprecated in efinity 2023.1.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
2c3536720c
efinix: ifacewriter: add `in_clk_inv` for GPIO INPUT block
...
add `in_clk_inv` for GPIO INPUT block.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
10ab1b76c0
efinix: ifacewriter: fix `out_reg` in GPIO INOUT block
...
fix `out_reg` in GPIO INOUT block.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
b135f71512
build/efinix/common: Disable SDRInput for now since breaking designs, needs to be investigated.
2024-09-26 12:58:54 +02:00
b5e91473b7
build/efinix/common: Update EfinixSDRInputImpl and minor cleanup.
2024-09-26 11:50:37 +02:00
0e337e2079
Merge pull request #2081 from VOGL-electronic/build_efinix_add_sdr_input
...
build: efinix: common.py; add `SDRInput`
2024-09-26 11:43:20 +02:00
a19fbb70c4
Merge pull request #2078 from VOGL-electronic/efinix_add_ipm
...
build: efinix: add function to add ip
2024-09-26 11:42:34 +02:00
b11cc8c3eb
Merge pull request #2082 from enjoy-digital/efinix_iface_signal_names
...
Efinix iface signal names.
2024-09-26 11:42:02 +02:00
39d292a3c7
build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names.
2024-09-26 10:38:05 +02:00
a3a55fc8fb
build/efinix/common: Directly pass ClockSignal/Signal to blocks and let the build resolve names.
2024-09-26 10:14:42 +02:00
fde9d2e4ad
build/efinix/efinity: Add resolve_iface_signal_names method to automatically resolve ClockSignal/Signal names passed in the blocks.
...
Allow the Migen/LiteX build elaboration to resolve signal names and just use it in blocks to avoid name_override workaround.
2024-09-26 10:13:58 +02:00
61f715e6e7
build: efinix: common.py; add `SDRInput`
...
add `SDRInput` for efinix
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-25 17:17:53 +02:00
c3e87367c3
soc/cores/vexriscv_smp: Add the generation of the default sim config ( https://github.com/litex-hub/linux-on-litex-vexriscv/issues/405 )
2024-09-25 10:38:37 +02:00
b86d76baed
build/sim/core/veril.cpp: Flush trace file on finish, fix issue with empty .fst dumps with short simulations.
2024-09-25 08:56:51 +02:00
8a6264c4f6
build: efinix: add function to add ip
...
add function to add efinix IP.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-24 11:59:28 +02:00
Florent Kermarrec
Dolu1990
Gwenhael Goavec-Merou
Massimo Gaggero
Fin Maaß