ce378f47d3
test/SyncFIFOCase: better test bench termination
2014-04-07 00:05:08 +02:00
ac1363565d
genlib/fifo: add SyncFIFOClassic and SyncFIFOBuffered
2014-04-05 12:15:14 +02:00
9deddbdfbc
test/test_cordic: fix for new Simulation API
2014-03-24 15:01:44 -07:00
7649028bdc
test/support: fix default ncycles
2014-03-24 15:01:44 -07:00
0023b742e4
genlib/coding: gracefully handle flen(i) < 2
2014-03-19 18:12:27 -07:00
0836f2814a
bus/csr: new simulation api
2014-03-19 18:12:27 -07:00
b03d9f4c14
genlib/fifo: add flush, expose level in SyncFIFO
...
AsyncFIFO would need versions of flush and level in each clock domain
plus some handshaking on double flush.
Signed-off-by: Robert Jordens <jordens@gmail.com>
2014-03-15 23:10:46 -07:00
2ab939e69d
fix SimActor TB terminations
2014-01-28 00:03:56 +01:00
90f0dfad63
Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator
2014-01-27 23:58:46 +01:00
63c1d7e4b7
New simulation API
2014-01-26 22:19:43 +01:00
8f69d9b669
bank/eventmanager: add SharedIRQ
2014-01-06 22:13:06 +01:00
be1c8551d2
migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime)
2013-12-17 18:40:49 +01:00
a20688f777
fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems
2013-12-13 00:02:50 +01:00
adda930c68
fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs
2013-12-12 17:37:31 +01:00
adffec35f6
utils/misc: add gcd_multiple function to compute GCD or any number of integers
2013-12-12 17:36:50 +01:00
c13fe1bc63
specials/Memory: allow for more flexibility in memory port signals
2013-12-12 17:36:17 +01:00
135a4fea25
fhdl/verilog: fix representation of negative integers
...
Give the explicit two's complement representation for the given bit width.
This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
2013-12-11 22:26:10 +01:00
d6cb981c7a
migen/test/test_signed: add a (currently failing) signed comparison testcase
2013-12-10 23:33:53 +01:00
487df5b174
migen/fhdl/bitcontainer: fix signed arrays (map is an iterator)
2013-12-10 23:32:12 +01:00
8d3d61ba98
fhdl.size: rename to bitcontainer
2013-12-03 22:51:52 +01:00
86ba9c8bbc
migen.fhdl.size: verify fslice for negative values
2013-12-03 21:39:37 +01:00
c71eb5778f
migen.fhdl.structure: have Cat() flat_iteration-ize its arguments
2013-12-03 21:36:33 +01:00
1bf133755e
migen.fhdl.tools: move flat_iteration to migen.util.misc as tools imports other things
2013-12-03 21:36:33 +01:00
fe67210d77
migen.fhdl.size: add fiter(), fslice(), and freversed()
...
do not overload __len__, __iter__, __reversed__ as not all valid
expressions (ints and bools) have them. furthermore len([]) is and
should be different from flen([]) (the later raises an error). keep
__getitem__ as an exception that proves the rule ;)
2013-12-03 21:36:33 +01:00
ae6b78faeb
genlib/divider: fix diff computation
2013-12-02 17:56:03 +01:00
dd24fdd356
genlib/sort: add bitonic, combinatorial sorter
...
complete with with api documentation and unittests
2013-12-02 12:56:36 +01:00
9762546c95
genlib/cordic: cleanup, documentation, unittests
2013-12-02 12:56:24 +01:00
e54fa6f5f4
migen/test: if SimCase is a TestCase, it's run in every module that imports it
2013-12-02 12:43:14 +01:00
4eef3b9399
migen/test/support: allow easy re-setUp of the testbench with different parameters
2013-12-02 12:42:59 +01:00
de830dc743
mibuild: use keyword arguments directly in build_cmdline
2013-12-01 17:56:07 +01:00
5b26fb10a9
genlib/coding: add docstrings, add it to api doc
2013-11-29 23:25:31 +01:00
5ccd1799f2
genlib/coding, test/test_coding: unittests
2013-11-29 23:25:03 +01:00
205908791a
test/test_fifo: do not use relative import
...
This way the test can simply be run with:
python -m unittest test_fifo.py
2013-11-29 23:18:03 +01:00
502a2871bc
test/test_fifo, genlib/fifo: move test to unittest
2013-11-29 23:11:53 +01:00
cb5e0953aa
migen/test: start unittests
2013-11-29 23:11:23 +01:00
55afab2276
sim: use Simulator as a contextmanager
...
__del__ garbage collector callbacks are too delicate. E.g. imported
modules can be garbage collected before the objects using them. Can't
use os.remove, socket.SHUT_RDWR...
* added a DeprecationWarning if a Simulator is garbage collected without
having its .close() called
* renamed all gc __del__ callbacks to close()
* implemented context manager hooks for Simulator. Use like
with Simulator(TestBench()) as s:
s.run()
2013-11-29 23:05:15 +01:00
be9fea182d
fhdl/structure: clarify usage restrictions of LHS Cat
2013-11-29 22:35:53 +01:00
73db4944f1
fhdl.structure: document the API
2013-11-29 22:31:55 +01:00
e469e5e539
genlib.fifo: fix docstring section syntax
2013-11-29 22:31:51 +01:00
e1b31ec455
genlib/fifo: clarify we behaviour when writable=0
2013-11-28 22:31:10 +01:00
6e9e0a60eb
setup API documentation, start by documenting fifos
2013-11-28 22:14:20 +01:00
fa741f54fd
specials/Instance: add PreformattedParam
2013-11-25 12:09:51 +01:00
29f7b94e37
bus/wishbone/sram: expose memory component
2013-11-24 23:43:14 +01:00
c5342c5b5c
bus/wishbone: style
2013-11-24 23:42:54 +01:00
948d7e7332
lasmibus/Crossbar: more flexible master assignment
2013-11-23 17:51:22 +01:00
7e4024beb3
genlib/fsm: rename {entering,leaving} to after_{entering,leaving}, add before_{entering,leaving}
2013-11-21 23:30:24 +01:00
cdabf34bee
flow/isd: update to new APIs
2013-11-20 17:45:09 +01:00
416c8af1e2
plumbing: use Record.connect in Multiplexer/ Demultiplexer
2013-11-04 21:22:05 +01:00
7e2859f43f
util: add missing __init__.py
2013-11-04 21:22:02 +01:00
c3aad93753
actorlib/spi/DMAWriteController: make ack_when_inactive a keyword-only arg
2013-11-02 23:21:05 +01:00
Robert Jordens
Sebastien Bourdeauducq
Florent Kermarrec