b0b57491bb
test_cpu: Add Microwatt to tested CPUs
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Now that LiteX can convert from VHDL to Verilog using GHDL, and the
required dependencies are installed in the CI environment, start testing
Microwatt.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-14 22:09:47 +10:30
f89746af9f
github: Add ppc64le toolchain
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The toolchain is used by microwatt.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-14 22:07:20 +10:30
25969237f5
github: Add GHDL to build environment
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GHDL provides a github action that adds a nightly build to the CI
environment:
https://github.com/ghdl/setup-ghdl-ci
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-14 22:07:20 +10:30
b340b86975
test_cpu: Set number of verilator jobs
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By default verilator will be built with -j with no arguments, spawning
many processors. This causes large designs to failure in CI (probably
due to exhausting the memory of the build box):
Error: Process completed with exit code 143.
Set the number of jobs to the number of CPUs in the system. This allows
designs such as Microwatt to build in CI.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-14 22:05:54 +10:30
05b0c59607
interconnect: For now remove the address_width checks; more verification will have to be done before enabling it to avoid regressions.
2022-11-14 10:34:48 +01:00
9115db5023
soc/cores/video/VideoS7GTPHDMIPHY: Fix typo (probably related to some refactoring).
2022-11-14 09:54:55 +01:00
ec126f0e4d
test/test_cpu: Move ibex to untested_cpus since seems to be broken since 2022.11.12.
2022-11-14 09:51:37 +01:00
269525862b
interconnect/axi/axi_lite_to_simple: Avoid combinatorial loop on ax.valid/ax.ready.
2022-11-14 09:34:10 +01:00
82127043c3
interconnect: Add data_width/address_width checks on InterconnectShared/Crossbar and also propagate address_width.
2022-11-14 09:08:28 +01:00
a3cc741d26
interconnect: Ensure data_width is propagated on all InterconnectShared/Crossbar modules.
2022-11-14 08:34:38 +01:00
68c34c64b0
Merge pull request #1501 from bunnie/axi-full-xbar-datawidth
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AXICrossbar: absorb data width setting when building crossbar
2022-11-14 08:24:23 +01:00
d741346f63
AXICrossbar: absorb data width setting when building crossbar
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This patch allows the AXICrossbar to absorb non-default datawidths
when the crossbar is built.
e.g. in the case of a 64-bit AXICrossbar, without this patch the
crossbar was only connecting the bottom 32 bits.
2022-11-12 18:29:51 +08:00
a7475d7f96
Merge pull request #1500 from cklarhorst/cd_fix
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core/naxriscv: Don't use os.system to execute sbt
2022-11-12 11:00:36 +01:00
c1c4910d67
core/naxriscv: Don't use os.system to execute sbt
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The use of os.system together with cd is a problem because it changes the
CWD for the whole python process. This breaks for example --csr-csv.
2022-11-11 14:14:47 +01:00
c1885b333f
build/altera/platform: Don't set keep attribute on clk signal when using add_period_constraints.
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This was preventing the build with Quartus.
2022-11-11 10:06:20 +01:00
62e869296f
build/generic_toolchain: Make adding keep attribute to clk signals optionals in add_period_constraint/add_false_path_constraint.
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Keep it enabled by default.
2022-11-11 10:05:30 +01:00
1a66f4a6ad
soc: Only do logging.BasicConfig when not already configured by top level script.
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Allow having a default logging and overriding it in user scripts.
2022-11-11 09:32:56 +01:00
d738eacf3d
build/parser: Add logging_group to configure logging (filename and level for now).
2022-11-11 09:32:48 +01:00
01b9ae7894
integration/soc: Convert sys_clk_freq to int in SoC to allow passing float to SoC.
2022-11-10 10:08:41 +01:00
7c7b7f7818
software/liblitedram: fix an off-by-1 error when write leveling
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When finding the longest 1 window when write leveling, if the last tap
is 1, it won't be correctly handle because the end condition force to
judge it as 0.
Add one more iteration and force 0 in that one to handle the last 1.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-10 11:40:21 +08:00
1e2ad2250d
compat/soc_core: Fix register_mem/rom missing imports.
2022-11-09 19:11:15 +01:00
7157b4c5e8
Merge pull request #1496 from MateuszKarlic/json2renode-update
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json2renode: Multicore configuration support
2022-11-09 15:52:31 +01:00
877dff8a09
soc/compat: Fix add_wb_slave compatibility that was no longer working correclty since finalization order changes.
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We should really remove this compatibility layer, but let's wait a bit to make
sure all designs are converted.
2022-11-09 15:40:09 +01:00
8a74eba4d5
software/liblitedram: scale up values when finding CMD delay
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The delay finding code is based on integers, and when divided by the
count, rounding error will be quite easy to happen.
Scale up all delay value by 256x to reduce rounding error.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-09 17:55:49 +08:00
a7a520695e
software/liblitedram: seek for consecutive delay range when centering
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On some boards, the working delay range found may be not so consecutive.
Considering this to be some inference, we should only count the biggest
consecutive delay range instead of just skip ahead for a fixed offset.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-09 17:50:34 +08:00
4a740651f0
litex_sim: Simplify configuration by creating a temporary config_soc that is then used for the configuration.
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This avoid several workarounds for CPU endianness, Bus data-width, RAM boot offset.
2022-11-09 09:24:30 +01:00
89afed5970
litex_sim: Switch to new LiteXArgumentParser and let it handle verilator build args.
2022-11-09 08:45:48 +01:00
c39d35de83
build/sim/platform: Add fill_args/get_argdict methods.
2022-11-09 08:45:12 +01:00
a2aa891baa
build/paltform: Minor cleanup on supported_toolchains/toolchain_group.
2022-11-09 08:44:49 +01:00
a2b5bb0db2
litex_sim: Switch from self.submodules to self.
2022-11-09 08:21:53 +01:00
d5df6e23f4
Merge pull request #1490 from Icenowy/litex-sim-membase-hack
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tools/litex_sim: hack to allow memory base other than 0x40000000
2022-11-09 08:18:50 +01:00
cd90e2623a
json2renode: cpu: Overhaul generate_cpu
2022-11-08 15:32:09 +01:00
eccb26874e
json2renode: cpu: Extract minor common logic
2022-11-08 15:32:09 +01:00
97772eb4bd
json2renode: IRQ: Fallback to cpu0 if plic is unavailable
2022-11-08 15:32:09 +01:00
4c959740dd
json2renode: Use cpu_count as local variable
2022-11-08 15:32:09 +01:00
b4bddc68e7
json2renode: Add LiteX MMCM
2022-11-08 15:32:09 +01:00
65964692dd
json2renode: Add auto-align hint
2022-11-08 15:32:09 +01:00
8b9ca8e9e9
json2renode: Silence false warnings about unsupported peripherals
2022-11-08 15:32:09 +01:00
283a237876
json2renode: Fix registration of GPIO peripherals
2022-11-08 15:32:09 +01:00
a9caeda30e
json2renode: Fix typo
2022-11-08 15:32:09 +01:00
55dcee16c3
json2renode: Use spiflash->base instead of flash_boot_address
2022-11-08 15:32:09 +01:00
860ca8673e
json2renode: Use opensbi->base for bios binary
2022-11-08 15:32:09 +01:00
ca63d12509
json2renode: Add support for multicore builds
2022-11-08 15:32:09 +01:00
240b24b7ff
gen/fhdl/hierarchy: Use [] for BlackBoxes.
2022-11-08 15:08:12 +01:00
b32d694ae4
interconnect/axi: Do not expose dest on AXI-Full (Only present for on AXI-Stream).
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We are using AXI-Stream for AXI-Full channels, so do an exception for dest signal.
2022-11-08 14:52:05 +01:00
f617e823b9
Merge pull request #1495 from Icenowy/openc906-debug
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cpus/openc906: add debug variant like vexriscv
2022-11-08 14:01:40 +01:00
85273ffe99
cpu/openc906: add debug variant that connects CPU DM to main bus
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The OpenC906 CPU core contains a RISC-V debug spec 0.13 compliant DM
with APB as its interface.
Add a CPU variant "debug" that will connect that APB to the main bus for
debugging.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-08 09:24:47 +08:00
9493338c68
cpu/openc906: fix the semantics of self.reset
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LiteX defaults to active-high reset signals, but OpenC906 uses
active-low ones, and the self.reset signal of openc906 module is wrongly
wired that it will force the CPU to run instead of force it to reset
(because it is ORed and then feed to the active-low reset line).
Fix this by using AND and inverting self.reset.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-08 09:24:47 +08:00
ff3bd11de1
Merge pull request #1494 from trabucayre/parset_fix_target_group
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litex/build/parser: check if self._target_group is not None before calling add_argument
2022-11-07 21:03:37 +01:00
98912f45e0
litex/build/parser: check if self._target_group is not None before calling add_argument
2022-11-07 20:40:09 +01:00
Joel Stanley
Florent Kermarrec
bunnie
Christian Klarhorst
Icenowy Zheng
Mateusz Karlic
Gwenhael Goavec-Merou