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9857 Commits

Author SHA1 Message Date
Florent Kermarrec 4ba3ad5409 sim/gtkwave: Update/fix SignalNamespace import (And make it public in fhdl/namer). 2023-11-09 10:29:43 +01:00
Florent Kermarrec 4b9c866d76 integration/soc/bus_addresing_convert: Simplify and skip on AXI/AXI-Lite interface since already handled in bridges. 2023-11-09 10:22:22 +01:00
Florent Kermarrec 03a0739d13 integration/soc/add_adapter: Use bus_ prefix for all converter functions for consistency. 2023-11-09 10:08:46 +01:00
Florent Kermarrec 53e458f63a integration/soc: Fix addressing order and remove limitations, we are now just limited to Wishbone. 2023-11-09 09:21:53 +01:00
Gwenhael Goavec-Merou 1ab85631b8 tools/litex_server, tools/remote/comm_udp: fix Etherbonexx constructors by passing addr_width/add_size 2023-11-09 07:07:48 +01:00
Florent Kermarrec 4610713797 gen/fhdl/verilog: Ensure top is not None to build hierarchy. 2023-11-08 16:58:23 +01:00
enjoy-digital 862a0dbbbf
Merge pull request #1829 from enjoy-digital/kianv 
cores/cpu: Add KianV CPU (RV32IMA) initial support.
 2023-11-08 11:43:07 +01:00
Florent Kermarrec 6598fe9c12 cores/cpu: Add KianV CPU (RV32IMA) initial support. 
litex_sim --cpu-type=kianv:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov  8 2023 11:14:03
 BIOS CRC passed (6984e675)

 LiteX git sha1: c1e4b3a8

--=============== SoC ==================--
CPU:		KianV-STANDARD @ 1MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> ident
Ident: LiteX Simulation 2023-11-08 11:14:00
litex>
 2023-11-08 11:37:22 +01:00
Gwenhael Goavec-Merou 93ce42f781 build/gowin/gowin: rework constraints: IOStandard & Misc in one line, merge _p/_n and only write _p 2023-11-07 20:44:37 +01:00
Gwenhael Goavec-Merou a0cb436467 build/gowin/common: adding Tristate support 2023-11-07 20:15:07 +01:00
Florent Kermarrec c1e4b3a850 xilinx/clock: Add reset_buf parameter to allow using a buffer to route reset signal. 2023-11-07 13:21:16 +01:00
enjoy-digital d0bb837b7c
Merge pull request #1828 from enjoy-digital/verilog_improvements_2 
Verilog improvements.
 2023-11-07 09:03:40 +01:00
Florent Kermarrec 657252c573 gen/fhdl/namer: Update copyrights. 2023-11-06 17:55:54 +01:00
Florent Kermarrec 5b989bcb0e gen/fhdl/verilog: Switch Assign/Operator types to IntEnum. 2023-11-06 17:24:03 +01:00
Florent Kermarrec 33fd7742c9 interconnect/stream/ClockDomainCrossing: Use DUID for clock_domain id to allow deterministic builds. 2023-11-06 16:49:54 +01:00
Florent Kermarrec ef4235a5d9 gen/fhdl/namer: Use _ for private functions and remove build_namespace. 2023-11-06 16:21:33 +01:00
Florent Kermarrec af508fddc5 gen/fhdl/namer: Improve/Simplify SignalNamespace.get_name method. 2023-11-06 15:54:19 +01:00
Florent Kermarrec 9ce29224a1 gen/fhdl/namer: Add all_numbers to HierarchyNode to avoid hasattr use. 2023-11-06 15:36:08 +01:00
Florent Kermarrec 3df23a27f5 gen/fhdl/namer: Avoid deep level of nesting on build_signal_name_dict_for_group. 2023-11-06 13:56:25 +01:00
Florent Kermarrec c8a96b8d79 gen/fhdl/namer: Add update method to HierarchyNode to replace update_hierarchy_node. 2023-11-06 13:52:02 +01:00
Florent Kermarrec c0057672d6 gen/fhdl/namer: Split build_signal_name_dict with build_hierarchical_name and update_name_dict_with_group. 2023-11-06 13:43:14 +01:00
Florent Kermarrec 0efccae8b4 gen/fhdl/namer: Simplify/Remove some redundancies. 2023-11-06 13:34:23 +01:00
Florent Kermarrec 16804acaa8 gen/fhdl/namer: Add update_hierarchy_node function to reduce build_hierarchy_tree complexity. 2023-11-06 13:19:19 +01:00
Florent Kermarrec 19a3ab2614 gen/fhdl/namer: Improve class/variable names. 2023-11-06 12:51:37 +01:00
Florent Kermarrec 9548259a5c gen/fhdl/namer: Simplify build_namespace and add comments. 2023-11-06 12:31:48 +01:00
Florent Kermarrec a65d471ed2 gen/fhdl/namer: Simplify _invert_pnd_build_signal_groups/_build_pnd and add comments. 2023-11-06 11:58:29 +01:00
Florent Kermarrec 36e47052b2 gen/fhdl/namer: Simplify _invert_pnd/_list_conflicting_signals/_set_use_number/_build_pnd_for_group and add comments. 2023-11-06 11:49:48 +01:00
Florent Kermarrec d28b7a1172 gen/fhdl/namer: Simplify _set_use_name/_build_pnd_from_tree and add comments. 2023-11-06 11:32:52 +01:00
Florent Kermarrec 6214aa69af gen/fhdl/namer: Simplify _build_tree and add comments. 2023-11-06 10:52:44 +01:00
Florent Kermarrec 1e805a8789 fhdl/namer: Remove debug and add docstring comments. 2023-11-06 09:38:17 +01:00
enjoy-digital 6aa22271f9
Merge pull request #1825 from enjoy-digital/verilog_improvements 
Verilog improvements
 2023-11-06 09:11:40 +01:00
enjoy-digital 2beeca4c95
Merge pull request #1827 from enjoy-digital/video_framebuffer_skip_first_frame 
cores/video/VideoFramebuffer: Skip first frame on enable to ensure pr…
 2023-11-06 09:11:26 +01:00
Florent Kermarrec b0c0669ed3 cores/video/VideoFramebuffer: Skip first frame on enable to ensure proper VTG/DMA synchronization. 2023-11-05 08:18:43 +01:00
Florent Kermarrec f4e68d78ca cores/video: Fix missing h/vsync connection in SYNC state. 2023-11-04 20:55:56 +01:00
Florent Kermarrec 6f431fa2b1 gen/fhdl: Cleanup/Simplify hierarchy generation. 2023-11-03 14:57:48 +01:00
Florent Kermarrec a1704a045e gen/fhdl/instance: Ident Parameters/IOs on max length of names. 2023-11-03 12:31:14 +01:00
Florent Kermarrec 4627e8958f gen/fhdl/instance: Generate Parameters/Inputs/Outputs/InOuts separators and generate IOs in Input/Output/InOut order. 2023-11-03 12:11:53 +01:00
Florent Kermarrec 18c0541e6a gen/fhdl/instance: Add instance description. 2023-11-03 11:53:32 +01:00
Florent Kermarrec 079a0a7b75 gen/fhdl/instance: First cleanup pass. 2023-11-03 11:47:07 +01:00
Florent Kermarrec dee64b346f gen/fhdl: Integrate Migen's Instance verilog generation to be able to customize it to our needs. 2023-11-03 11:40:16 +01:00
Florent Kermarrec fe19ee464e gen/fhdl/memory: Rename memory_emit_verilog to _memory_generate_verilog. 2023-11-03 11:29:48 +01:00
Florent Kermarrec e6d950bcb0 gen/fhdl/verilog: Add module hierarchy generation after module definition. 
Will give a better overview of the generated verilog and will also ease comparing changes/track regressions.
 2023-11-03 11:08:40 +01:00
Florent Kermarrec 4a1486b1db gen/fhdl/hierarchy: Add with_colors parameters to allow enabling/disabling colors. 2023-11-03 11:06:41 +01:00
Florent Kermarrec 4497569118 gen/context: Rename soc to top. 2023-11-03 11:05:57 +01:00
Florent Kermarrec 27c55999c6 gen/common/colorer: Add enable parameter to allow enabling/disabling coloring. 2023-11-03 11:05:09 +01:00
Florent Kermarrec 1f200c83f3 build: Minor cleanups on get_verilog calls. 2023-11-03 11:04:31 +01:00
Florent Kermarrec b60bd92533 gen/fhdl/verilog: Rename _print_xy to _generate_xy and cleanup imports. 2023-11-03 10:14:38 +01:00
enjoy-digital 71ae8fe828
Merge pull request #1824 from trabucayre/add_64_bus_support_v2 
soc/interconnect/wishbone: InterconnectShared,Crossbar: using master adr_width for Interface constructor
 2023-10-31 21:17:31 +01:00
Gwenhael Goavec-Merou 755808e287 soc/interconnect/wishbone: InterconnectShared,Crossbar: using master adr_width for Interface constructor 2023-10-31 11:59:49 +01:00
Florent Kermarrec 9b8a5b6385 CHANGES: Update. 2023-10-30 19:40:42 +01:00