Sebastien Bourdeauducq
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94b02aa8ed
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bus/asmicon: initiator
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2012-03-30 22:16:31 +02:00 |
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Sebastien Bourdeauducq
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bb864c65dc
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sim: proxy
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2012-03-30 16:40:26 +02:00 |
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Sebastien Bourdeauducq
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081b658e2d
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Update copyright notices
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2012-03-23 16:41:30 +01:00 |
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Sebastien Bourdeauducq
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d47b564fad
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corelogic/fsm: typo
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2012-03-18 22:12:46 +01:00 |
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Sebastien Bourdeauducq
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5f28103769
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corelogic/fsm: delayed enters
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2012-03-18 00:09:40 +01:00 |
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Sebastien Bourdeauducq
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a4294762d0
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corelogic/roundrobin: CE switching
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2012-03-16 16:54:47 +01:00 |
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Sebastien Bourdeauducq
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e969b9afc3
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corelogic: convert timeline to function and move to misc
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2012-03-15 20:25:44 +01:00 |
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Sebastien Bourdeauducq
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1665f293a6
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bus/asmibus/hub: require finalization before get_slots
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2012-03-14 16:19:29 +01:00 |
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Sebastien Bourdeauducq
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5c0cc6292c
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fhdl: export log2_int
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2012-03-14 12:19:42 +01:00 |
Alain Péteut
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97fece249d
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setup.py: simplify
Signed-off-by: Alain Péteut <alain.peteut@yahoo.com>
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2012-03-11 00:52:13 +01:00 |
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Sebastien Bourdeauducq
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f6e76ae198
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doc: more examples and comments
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2012-03-10 19:38:39 +01:00 |
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Sebastien Bourdeauducq
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1f4c58ee26
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doc: cosmetic changes (thanks sh4rm4 for reporting typos)
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2012-03-10 17:59:42 +01:00 |
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Sebastien Bourdeauducq
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78c707e354
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doc: use script font
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2012-03-09 21:57:50 +01:00 |
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Sebastien Bourdeauducq
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7b1101ab99
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doc: simulation
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2012-03-09 21:17:21 +01:00 |
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Sebastien Bourdeauducq
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0165d23295
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doc: cosmetic changes (thanks rofl0r for reporting typos)
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2012-03-09 18:26:00 +01:00 |
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Sebastien Bourdeauducq
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59db4e9106
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doc: add logo
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2012-03-09 17:16:33 +01:00 |
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Sebastien Bourdeauducq
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90546fd811
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doc: switch to sphinx
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2012-03-09 17:08:38 +01:00 |
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Sebastien Bourdeauducq
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57a87b3316
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examples: FIR filter simulation
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2012-03-08 20:49:36 +01:00 |
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Sebastien Bourdeauducq
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bfcd4e636b
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fhdl: handle negative constants correctly
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2012-03-08 20:49:24 +01:00 |
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Sebastien Bourdeauducq
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f4adb0fe9c
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examples: remove outdated wb_intercon simulation
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2012-03-08 18:17:56 +01:00 |
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Sebastien Bourdeauducq
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84aa703447
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vpi: support extra include directories
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2012-03-08 18:14:40 +01:00 |
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Sebastien Bourdeauducq
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bbaadebf68
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gitignore: update
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2012-03-08 18:14:19 +01:00 |
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Sebastien Bourdeauducq
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ab800fa2ed
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bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
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Sebastien Bourdeauducq
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ddc0e49981
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vpi: patch for Icarus Verilog
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2012-03-08 17:27:59 +01:00 |
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Sebastien Bourdeauducq
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59a57e7a76
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examples: small cleanup
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2012-03-08 15:55:02 +01:00 |
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Sebastien Bourdeauducq
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678a89d572
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sim: fix zero encoding
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2012-03-08 15:34:08 +01:00 |
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Sebastien Bourdeauducq
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decbd069fa
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sim: fix message debug formatting
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2012-03-08 15:27:35 +01:00 |
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Sebastien Bourdeauducq
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98e96b3952
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sim: make initialization cycle optional (selectable by function attribute)
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2012-03-06 19:43:59 +01:00 |
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Sebastien Bourdeauducq
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8160ced2e9
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sim: memory access
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2012-03-06 19:29:39 +01:00 |
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Sebastien Bourdeauducq
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db8f8bf2e3
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fhdl: register memory objects with namespace
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2012-03-06 18:33:44 +01:00 |
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Sebastien Bourdeauducq
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6f829c7afc
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sim: support for signed numbers
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2012-03-06 16:46:18 +01:00 |
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Sebastien Bourdeauducq
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90184b22d2
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fhdl/verilog: fix signed constant conversion
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2012-03-06 16:45:44 +01:00 |
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Sebastien Bourdeauducq
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0a23cadd38
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vpi: install target
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2012-03-06 15:51:09 +01:00 |
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Sebastien Bourdeauducq
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9da512dbf5
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sim: VCD generation
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2012-03-06 15:26:04 +01:00 |
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Sebastien Bourdeauducq
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22b3c11b93
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sim: clean startup/shutdown
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2012-03-06 15:00:02 +01:00 |
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Sebastien Bourdeauducq
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06de17b16c
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sim: remove temporary files and socket
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2012-03-06 14:20:26 +01:00 |
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Sebastien Bourdeauducq
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7230508e7c
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fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
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2012-03-06 14:18:22 +01:00 |
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Sebastien Bourdeauducq
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2c375e900f
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sim: remove default sockaddr
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2012-03-06 13:58:49 +01:00 |
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Sebastien Bourdeauducq
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8d16fde48c
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fhdl: add simulation functions in fragment
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2012-03-06 13:58:22 +01:00 |
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Sebastien Bourdeauducq
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aac9752558
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sim: basic functionality working
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2012-03-05 20:31:41 +01:00 |
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Sebastien Bourdeauducq
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c4c22c9ca0
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sim: signal writes working
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2012-03-05 15:40:21 +01:00 |
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Sebastien Bourdeauducq
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9bbec278c6
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sim: cleanups
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2012-03-04 22:56:56 +01:00 |
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Sebastien Bourdeauducq
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2cd71e4b5e
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sim: signal reads working
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2012-03-04 22:33:03 +01:00 |
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Sebastien Bourdeauducq
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c0b0161ec9
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sim: compile VPI module
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2012-03-04 21:27:02 +01:00 |
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Sebastien Bourdeauducq
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29859acc34
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sim: two way IPC working
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2012-03-04 19:17:03 +01:00 |
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Sebastien Bourdeauducq
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8586daf2dd
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sim: IPC module (lacks str/int encoding)
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2012-03-03 18:55:38 +01:00 |
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Sebastien Bourdeauducq
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7f307c54a9
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README: clarify license
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2012-02-29 20:30:08 +01:00 |
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Sebastien Bourdeauducq
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1b8cb5b46c
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bus/dfi: fix multiphase naming
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2012-02-19 17:57:04 +01:00 |
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Sebastien Bourdeauducq
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d8d4e81b6e
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bank/csrgen: fix RE generation
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2012-02-18 18:56:18 +01:00 |
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Sebastien Bourdeauducq
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55a265d967
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bank: add RE signal for registers made of fields
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2012-02-17 23:52:06 +01:00 |