3d101b9749
integration/export: When csr_base is specified, make CSR regions definition relative to it.
...
Useful for PCIe based systems when internal CSR base is automatically added by the logic.
2023-07-17 11:14:33 +02:00
3fc16f54f1
soc/cores/cpu: Switch to LiteXModule.
2023-07-17 09:26:58 +02:00
39ff69ade7
cores/spi: Switch to LiteXModule.
2023-07-17 09:14:47 +02:00
028f7eb72f
cores/ram: Switch to LiteXModule.
2023-07-17 09:12:25 +02:00
b35c6580e8
soc/cores/clock: Switch to LiteXModule.
2023-07-15 21:54:07 +02:00
8103cf7851
soc/cores: Switch cores to LiteXModule (still need to do cpu, ram, clk, spi).
2023-07-14 22:19:14 +02:00
6e46710678
gen/fhdl/module: Fix CSR clock domain renaming to cores converted to LiteXModule, thanks @smunaut.
2023-07-14 10:01:32 +02:00
987a35e1ec
Merge pull request #1729 from riktw/master
...
Currently using a lite or minimal Vexriscv config with debug and brea…
2023-07-13 15:21:51 +02:00
3a2586c48b
soc/add_pcie: Remove csr_ordering parameter (not useful and remove on litepcie).
2023-07-12 19:42:54 +02:00
f9e32eb3eb
CHANGES: Update.
2023-07-11 16:42:21 +02:00
eb1afbad47
Currently using a lite or minimal Vexriscv config with debug and breakpoints throws an error. Updated the GCC_FLAGS to include these two variants as well.
2023-07-11 16:16:51 +02:00
26732f626f
CHANGES: Update.
2023-07-10 11:24:49 +02:00
d18c6316f4
gen/fhdl/verilog: Improve signal sort by name instead of duid to improve reproducibility.
2023-07-10 11:24:46 +02:00
698b4dd875
Merge pull request #1728 from stone3311/master
...
cores/arm: Fix computed goto in boot helpers
2023-07-10 08:31:07 +02:00
42c422e767
cores/arm: Fix computed goto in boot helpers
2023-07-09 19:16:06 +02:00
e62f51c3eb
gen/genlib/cdc: Add missing import.
2023-07-07 11:51:04 +02:00
2b941cdcd9
gen/genlib: Add copy of genlib.cdc modules that we are using and not supported by Amaranth to prepare #1727 .
2023-07-06 22:23:54 +02:00
e9739b5446
soc: Switch to litex.gen.genlib.misc.
2023-07-06 22:05:23 +02:00
6f98053b1a
litex/gen: Add copy of genlib.misc to prepare for #1727 .
2023-07-06 22:03:41 +02:00
ec43ca77ed
Merge pull request #1724 from stone3311/master
...
cores/zynqmp: Fix boot helper
2023-07-06 09:15:13 +02:00
54f466772b
cores/zynqmp: Fix boot helper
2023-07-05 20:14:05 +02:00
c58f46bb79
CHANGES: Update.
2023-07-03 18:09:56 +02:00
a2d44370bd
CHANGES: Update.
2023-07-03 10:56:29 +02:00
7fa7a4c72a
soc/add_ethernet: Review/Minor changes to TXSlots write-only mode.
2023-07-03 10:50:47 +02:00
646c917d7f
Merge pull request #1720 from sensille/tx_write_only
...
Tx write only
2023-07-03 10:45:52 +02:00
886994aaa4
Merge pull request #1721 from rasmuspeders1/master
...
Make litex_json2renode work with default arty target SOC .json file
2023-06-30 10:05:45 -07:00
26ed13a300
Assume cpu count 1 if not present
2023-06-30 13:46:08 +02:00
8d33dc364f
Only add "cpu PC <opensbi_base>" if opensbi is present
2023-06-30 13:44:31 +02:00
a12703b4ee
litex_json2renode: only add cpu timeProvider if time_provider exists
2023-06-29 14:13:49 +02:00
648c70de82
cmd_litesata: Fix help printf and update CHANGES.
2023-06-28 23:07:17 +02:00
b7cbd6c7fb
Merge pull request #1715 from gsomlo/gls-sata-multisector
...
Update bios for LiteSATA multi-sector read/write changes
2023-06-28 23:03:15 +02:00
74c3ba0992
Merge branch 'enjoy-digital:master' into tx_write_only
2023-06-28 18:56:05 +02:00
2cdc4fb0ab
ci: Use last known working version of Verilator for Microwatt (Thanks @trabucayre).
2023-06-27 14:32:31 +02:00
5524a17702
add tx_write_only flag to add_ethernet
...
This can save some resources in case reading the tx buffer is not needed.
It also makes it easier for synthesis to infer BRAM, tested on Spartan6.
2023-06-27 09:45:50 +02:00
7a7c74faa9
fix radiant bug 'Mal-formed command line - please check for extra quotes in macro' ( #1718 )
...
* fix radiant bug 'Mal-formed command line - please check for extra quotes in macro'
* fix Radiant Mal-formed command line bug (more pythonic)
* (typo, rm line 159) fix Radiant Mal-formed command line bug
---------
Co-authored-by: slagernate@github.com <slagernate@github.com>
2023-06-24 08:57:44 +02:00
8dca488432
software/bios/cmd_litesata: add multisector read/write test
2023-06-22 17:59:18 -04:00
1d2eddbe37
software/bios/cmd_litesata: add multi-sector xfer between SATA and memory
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-06-22 17:59:18 -04:00
7d1e12c870
software/liblitesata: update to multi-sector read, write
...
The LiteSATA gateware now supports multi-sector transfers, and expects
a sector count register to be populated by the software before a DMA
transfer is initiated.
This patch also fixes checks for `done` and `error` during writes by
using the correct `mem2sector` read function (instead of `sector2mem`,
which is for use during read operations).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-06-22 17:59:18 -04:00
a9d6a0c6c9
CHANGES: Update.
2023-06-22 17:40:41 +02:00
fbe3fcf76a
CHANGES: Update.
2023-06-21 12:46:16 +02:00
7b5515ced4
cores/pwm: Simplify pwm generation and avoid potential glitch on reset.
2023-06-19 23:02:50 +02:00
298ec03dae
Merge pull request #1713 from shenki/microwatt-socregion
...
microwatt: Correct SoCRegion typo
2023-06-19 19:23:11 +02:00
d2aae18957
soc/add_pcie/MSI-X: Pass csr_ordering to LitePCIeMSIX.
2023-06-19 19:21:05 +02:00
94a0a5b0d8
soc/add_pcie: Add msi_width parameter to select MSI width.
2023-06-19 09:54:56 +02:00
a9cbb16785
soc/add_pcie: Add msi_type parameter to select MSI, MSI-Multi-Vector or MSI-X.
2023-06-19 09:45:21 +02:00
ae22f4028a
microwatt: Correct SoCRegion typo
...
Fixes: 45b9636902
2023-06-18 21:56:31 +09:30
6e5651b320
CHANGES: Update.
2023-06-16 08:33:23 +02:00
56927ee73a
cpu/vexriscv_smp/core: Add add_synthesis_define function to add 'define SYNTHESIS to VexRiscv-SMP generated code for toolchains requiring it.
...
This was causing issue with Gowin synthesis tool and it's not yet clear how to define it from Gowin project.
So do it directly in the generated code for now until we find a better solution.
See https://github.com/enjoy-digital/litex/issues/1698 .
2023-06-15 15:45:34 +02:00
3d3ca05359
tools/litex_client: Fix read regression.
2023-06-14 16:59:47 +02:00
7a4fa58cbf
CHANGES: Update.
2023-06-13 18:37:34 +02:00
Florent Kermarrec
Dolu1990
riktw
stone3311
Gwenhael Goavec-Merou
Tim 'mithro' Ansell
Rasmus Pedersen
Arne Jansen
Nate Slager
Gabriel Somlo
Joel Stanley