Commit Graph

6952 Commits

Author SHA1 Message Date
Florent Kermarrec 6fc87f7c85 build/gowin/common: Add DDRInput/DDROutput implementations. 2021-07-14 10:01:54 +02:00
Florent Kermarrec a8cea15b95 cores/clock/gowin_gw1n/create_clkout: Add reset support (through AsyncResetSynchronizer) and enable it by default.
Should be based on PLL's lock but does not seem stable, so use reset input for now.
2021-07-14 09:38:23 +02:00
Florent Kermarrec cfbc06c297 build/gowin/common: Add AsyncResetSynchronizer implementation. 2021-07-14 09:37:00 +02:00
enjoy-digital fab6512928
Merge pull request #967 from JosephBushagour/jbushagour_assembly_interoperability
Make "generated/soc.h" able to be included in assembly files.
2021-07-13 10:47:59 +02:00
enjoy-digital df67b65a0a
Merge pull request #957 from pftbest/fix_fst
Fix compile error when FST traces are enabled on macOS.
2021-07-13 10:38:40 +02:00
Joey Bushagour c79e428fe1 Add soc.h interoperability with assembly. 2021-07-12 08:33:17 -05:00
Florent Kermarrec bc77aa37f0 include/hw/common: Fix _csr_rd_buf/_csr_wr_buf for sizeof(buf[0]) < CSR_DW_BYTES case.
- Shift in _csr_rd_buf should only been done when buf is set.
- When CSR size is not an exact multiple of the CSR data-width, the gap is in
the low addresses, not the high ones. So offset is introduced to take this into
account.
2021-07-09 17:36:17 +02:00
Florent Kermarrec b29a99cd0b liblitedram/sdram.c: Fix DFII_PIX_DATA_BYTES computation.
DFII CSR size is not necessarily multiple of 4 (often the case but not with ECC for example).
2021-07-09 17:32:43 +02:00
Florent Kermarrec 2b49430f2c README.md: Rewrite Welcome section and update copyright. 2021-07-08 12:08:24 +02:00
Florent Kermarrec 9a51dfb50e tools/litex_sim: Let the SDRAMPHYModel pick default settings. 2021-07-08 09:09:57 +02:00
Florent Kermarrec fced79631e tools/litex_sim: sdram_module_nphases/get_sdram_phy_settings now directly integrated in litedram.phy.model. 2021-07-08 09:01:32 +02:00
enjoy-digital dd5413bc9f
Merge pull request #964 from niw/increase_macos_ttyusbmodem_delay
Increase delay for `tty.usbmodem` on macOS.
2021-07-06 18:51:28 +02:00
Yoshimasa Niwa 0953c52eea Increase delay for `tty.usbmodem` on macOS.
**Problems**

On macOS USB CDC ACM, which appears as `/dev/tty.usbmodem*`,
somehow `lxterm` keeps failing to send a payload.

**Solution**

Increase delay.

It's very unknown why to me, however, probably macOS USB CDC ACM
driver implementation issue.

**Testing**

Tested on MacBook Air (2020, M1) for OrangeCrab (rev.0.2) target
with Linux on LiteX SoC bitstream build from current commit and
load prebuild Linux On LiteX image.
2021-07-05 11:46:57 -07:00
Florent Kermarrec f9f1b8e25d liblitedram: Consider 1s window is valid when indirectly seen before 0 (start at 0 and long enough). 2021-06-29 12:03:51 +02:00
enjoy-digital 8192ad335f
Merge pull request #958 from sergachev/master
soc/interconnect/axi: fix valid signal in connect_to_pads for axi lite
2021-06-28 17:37:29 +02:00
Ilia Sergachev 65babd6500 soc/interconnect/axi: fix valid signal in connect_to_pads for axi lite 2021-06-28 11:50:45 +02:00
enjoy-digital 4d959bbc81
Merge pull request #956 from developandplay/simplify-blackparrot-setup
Simplify blackparrot setup
2021-06-28 11:26:50 +02:00
Vadzim Dambrouski 35204225e8 Fix compile error when FST traces are enabled on macOS.
Compile options should be the same for all platforms.
2021-06-27 17:34:43 +03:00
developandplay 9fd9eaea07 Move patch script to python-data 2021-06-27 01:31:05 +02:00
developandplay ac217d818f Set environmental variables in python 2021-06-27 01:07:27 +02:00
developandplay e3f6d8349b Use os methods to expand env vars 2021-06-26 16:30:54 +02:00
developandplay b787ee4411 Move systemverilog files to python-data 2021-06-26 15:45:48 +02:00
developandplay 16b3e08c17 Copy config loader in python 2021-06-26 15:37:17 +02:00
enjoy-digital 23afca3de8
Merge pull request #953 from developandplay/blackparrot-32bit-csr
Blackparrot 32bit csr
2021-06-23 19:20:51 +02:00
Florent Kermarrec edc4c85615 build/lattice/common: Add ECP5 Differential Output support. 2021-06-23 11:55:22 +02:00
developandplay adb71bde8c Adjust wishbone adapter for 32bits 2021-06-22 23:37:24 +02:00
developandplay b795f848a2 Fixup blackparrot 2021-06-22 18:43:17 +02:00
Florent Kermarrec c395a8068a cores/prbs: Minor Cleanup and make sure to generate errors when RX is Idle. 2021-06-22 16:57:00 +02:00
Florent Kermarrec 2cd6224acf clock/lattice_ecp5/ECP5PLL: Add expose_dpa method (Dynamic Phase Adjustment) and move code to it. 2021-06-22 12:07:39 +02:00
enjoy-digital 09a3ca6fd0
Merge pull request #949 from zyp/ecp5_dynamic_pll
cores/clock/ecp5: Add dynamic phase adjustment signals.
2021-06-22 12:04:20 +02:00
enjoy-digital 26df3fa2c4
Merge pull request #952 from smunaut/dfu
build/DFUProg: Allow to specify alt interface and to not reboot
2021-06-22 12:03:43 +02:00
Florent Kermarrec 3d81c9a437 build/lattice/LatticeProgrammer: pgrcmd always seems to return a non-zero value so disable check. 2021-06-22 11:59:42 +02:00
Florent Kermarrec f381cdcd1a build/GenericProgrammer: Add check parameter to make check optional. 2021-06-22 11:59:38 +02:00
Sylvain Munaut 38e46bb3d3 build/DFUProg: Allow to specify alt interface and to not reboot
Some targets have multiple alt settings for DFU for different zone
of the flash. Allowing to specify which one to flash and not
rebooting immediately allows to flash several of them at once.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-06-21 16:12:55 +02:00
Florent Kermarrec d6f24f2f68 cores/uart/RS232ClkPhaseAccum: Avoid reset on phase signal, improve timings/resources on iCE40. 2021-06-20 14:33:25 +02:00
Florent Kermarrec 4c8184fbb6 cores/uart: Fix refactoring typo (tick is a 1-bit Signal), thanks @tnt. 2021-06-20 08:58:45 +02:00
Vegard Storheil Eriksen b58c416a24 cores/clock/ecp5: Add dynamic phase adjustment signals. 2021-06-19 11:24:08 +02:00
enjoy-digital e7d04a2d1b
Merge pull request #948 from developandplay/non-interactive
Expose non-interactive mode
2021-06-18 13:27:18 +02:00
developandplay 7d2e19ac26 Enable non-interactive mode 2021-06-18 12:35:42 +02:00
enjoy-digital fdb278838c
Merge pull request #881 from developandplay/patch-1
Add --non-interactive option to simulation
2021-06-18 10:40:19 +02:00
Florent Kermarrec 5205356d24 tools/litex_json2dts: Simplify Switches interrupt support (and make it similar to other interrupts). 2021-06-18 10:36:33 +02:00
enjoy-digital 291374e66f
Merge pull request #854 from mczerski/gpio_dts_irq
dts: gpio: interrupt controller definition for switches
2021-06-18 10:29:30 +02:00
Florent Kermarrec 98676162a3 VexRiscv-SMP: Review/Cleanup #906. 2021-06-18 10:19:27 +02:00
enjoy-digital 58c533668c
Merge pull request #906 from rdolbeau/extra_config_and_dts
Configurable [ID]TLB for VexRiscv & improved DTS
2021-06-18 10:09:28 +02:00
Florent Kermarrec 8ce7c583e6 cores/spi: Add Manual CS Mode (to allow doing Bulk Xfers without external changes), also cleanup/simplify a bit CSR descriptions. 2021-06-18 10:07:01 +02:00
Florent Kermarrec ac73474d66 CONTRIBUTORS: Update. 2021-06-17 23:23:06 +02:00
Florent Kermarrec a4be067d91 tools: Add litex_contributors.py script to easily update CONTRIBUTORS file. 2021-06-17 23:04:28 +02:00
Florent Kermarrec 7179d88e8c ram/lattice_nx: Add init parameter and rename method to add_init.
When init is not empty, call add_init automatically (similar to Memory).
2021-06-16 18:33:00 +02:00
enjoy-digital 869b5c24a8
Merge pull request #941 from danc86/nxlram-initval
soc/cores/ram: allow populating initial values in Nexus LRAM
2021-06-16 18:31:00 +02:00
enjoy-digital b0e6851150
Merge pull request #942 from zyp/external_software_packages
Allow external software packages to be linked into the BIOS
2021-06-16 18:21:55 +02:00