411e6ec114
fhdl/tools: do not export resort_statements
2013-07-17 16:50:09 +02:00
d5d2e64dc3
Revert "fhdl/tools/group_by_target: remove resort_statements"
...
This reverts commit 939f01cee2
2013-07-17 16:49:26 +02:00
ea65aaaddd
s6ddrphy: cleanup
2013-07-17 13:58:58 +02:00
da2b7aa961
cif: fix indentation
2013-07-17 13:54:05 +02:00
fb06d803e1
s6ddrphy: revert CAS LATENCY 3 (configurable CAS Latency was buggy)
2013-07-17 13:11:25 +02:00
525c32976b
software/memtest: fix bandwidth computation
2013-07-17 13:08:40 +02:00
9190568685
genlib/fifo/AsyncFIFO: fix data corruption bug
2013-07-17 12:10:39 +02:00
939f01cee2
fhdl/tools/group_by_target: remove resort_statements
2013-07-17 10:38:39 +02:00
16ebe41028
fhdl/tools: BUGFIX: fix group_by_target grouping
...
group_by_target does not properly combine target groups if statements
are presented in the order:
({A}, statement1)
({B}, statement2)
({A, B}, statement3)
which returns groups:
({A, B}, [statement1, statement3])
({B}, [statement2])
This patch fixes group_by_target such that the resulting group is:
({A, B}, [statement1, statement2, statement3])
2013-07-17 10:14:39 +02:00
5b36f688ea
Remove ASMI
2013-07-16 18:50:50 +02:00
7e3b84ad36
framebuffer: remove workaround for asyncfifo bug
2013-07-16 18:49:35 +02:00
faa8b7c49a
fhdl/tools: clock domain merging for clock renaming
2013-07-16 18:17:44 +02:00
b016a60b85
lasmibus: fix master locking
2013-07-15 21:45:07 +02:00
7083764b53
genlib/fifo: add test bench
2013-07-15 21:36:39 +02:00
8c44c72499
tb/lasmicon: add DF test
2013-07-15 21:34:53 +02:00
90fecb920c
memtest: use actual values in TB
2013-07-15 21:34:14 +02:00
7ce2031d07
lasmicon/bankmachine: remove stale import
2013-07-15 17:46:18 +02:00
a0f1ee3fbb
lasmicon: update test benches
2013-07-15 17:45:55 +02:00
d753c52225
lasmicon: fix FSM reset state with delayed_enter
2013-07-15 00:57:37 +02:00
2f662bf8ab
software/videomixer: fix overflow in memory bandwidth computation
2013-07-14 20:05:18 +02:00
f3e07db1ef
software/memtest: basic test
2013-07-13 17:31:46 +02:00
65a0b12812
actorlib/spi/DMAController: export length/storage/trigger
2013-07-13 17:13:15 +02:00
6595b9a111
actorlib/spi/SingleGenerator: export CSRs
2013-07-13 17:12:51 +02:00
9ab22fe3b1
memtest/MemtestWriter: fix 'busy status stuck' bug
2013-07-13 17:11:23 +02:00
c2d6f14087
flow/actor/PipelinedActor: clean up
2013-07-12 18:52:34 +02:00
3d899f04fd
cif : fix 2x autorefresh in get_sdram_phy_header
2013-07-12 15:39:14 +02:00
6aa1e0c199
actorlib/spi/DMAWriteController: len -> flen
2013-07-11 19:22:56 +02:00
379a48bb31
software: add memtest
2013-07-11 19:03:45 +02:00
e42a42ce40
software: move time.c to libbase
2013-07-11 19:00:48 +02:00
c2ec077d8f
software: share SDRAM linker script
2013-07-11 18:49:42 +02:00
25506c1ab5
software: share crt0
2013-07-11 18:36:26 +02:00
aa5cdd5e67
make: add option to include memtest cores
2013-07-11 18:32:05 +02:00
be40cf178c
top: integrate memtest cores
2013-07-11 18:31:51 +02:00
3162949f82
memtest: add DMA cores
2013-07-11 18:31:38 +02:00
805432bec7
memtest/LFSR: test bench
2013-07-11 16:23:05 +02:00
d3bbbded0f
cif.py: use format instead of % in get_sdram_phy_header
2013-07-11 10:08:21 +02:00
a7a7cc0b95
memtest: LFSR
2013-07-10 21:08:57 +02:00
26ff6f2a9c
s6ddrphy: style and other minor fixes
2013-07-10 20:39:53 +02:00
f5ddd33e7e
dfi: split phase description
2013-07-10 19:56:47 +02:00
60f1585fef
use Migen s6ddrphy, generate sdram init_sequence in cif.py
2013-07-10 19:56:09 +02:00
9d9270b5cd
dvisampler: report FIFO overflow
2013-07-10 19:55:36 +02:00
1d33c61308
examples/sim/abstract_transactions_lasmi: check data
2013-07-10 19:11:02 +02:00
43fe16ef73
bus/lasmibus: add separate req/data ack to target and initiator
2013-07-10 19:09:51 +02:00
af6ef0a3b4
dma_lasmi/Writer: fix default FIFO depth
2013-07-07 20:01:55 +02:00
fa8112c3f5
dma_lasmi/Reader: handle ack=1 when stb=0
2013-07-07 18:57:05 +02:00
7e6fbd31a4
lasmibus/crossbar: simplify master ack generation
2013-07-07 18:56:43 +02:00
d0b21469e5
make: fix byteswap invocation
2013-07-07 14:55:06 +02:00
b18cffb5e8
xilinx_ise: run tools like Project Navigator does to avoid weird bitgen behavior
2013-07-04 23:49:12 +02:00
05bc2885e9
Call finalize() after CRG creation
2013-07-04 19:49:39 +02:00
71c2c5813b
platforms/mixxeo: remove bank 3 DVI inputs
2013-07-04 19:27:28 +02:00
Sebastien Bourdeauducq
Florent Kermarrec
David Carne