d34b7d7a6b
mibuild/xilinx: remove obsolete CRG_DS
2015-03-14 00:27:24 +01:00
6a979a8023
mibuild: sanitize default clock management
2015-03-14 00:10:08 +01:00
702d177c85
mibuild: get rid of Platform factory function, cleanup
2015-03-13 23:25:15 +01:00
ff266bc2ee
migen/genlib/io: add DifferentialOutput and Xilinx implementation
2015-03-12 19:30:57 +01:00
bf28664cb4
genlib/io.py: fix copy/paste error (thanks rjo)
2015-03-12 18:49:49 +01:00
c8ba8cde8e
migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild
2015-03-12 18:38:53 +01:00
00e8616de2
mibuild/sim: clean up (thanks sb)
2015-03-10 16:41:52 +01:00
555c444da2
mibuild/sim/dut_tb: fix permissions
2015-03-10 11:06:55 +01:00
9d8f1cd61d
mibuild/sim: get serial dev from /tmp/simserial
2015-03-10 00:42:54 +01:00
70a3e8081c
mibuild/sim: add support for pty
2015-03-09 23:31:11 +01:00
aa609bee15
mibuild/sim: remove hack, the issue was in gateware (padding)
2015-03-09 20:57:20 +01:00
8e09a86e4f
genlib/misc: add increment parameter to Counter
2015-03-09 20:20:25 +01:00
ebcea3c000
fhdl/module: use r.append() in _collect_submodules
2015-03-09 19:45:02 +01:00
ee1091f491
fhdl/module: avoid flushing self._submodules and create do_exit.
2015-03-09 17:17:21 +01:00
efc5f221d9
mibuild/sim: clean up and move eth struct to sim
2015-03-09 14:40:33 +01:00
a72c091bc2
mibuild/sim: regroup console_tb/ethernet_tb in dut_tb
2015-03-09 14:40:31 +01:00
e82b540a96
mibuild/sim: remove server and interact with tap directly in cpp tb. for now: - need to create tap manually: create tap: openvpn --mktun --dev tap0 ifconfig tap0 192.168.0.14 up mknod /dev/net/tap0 c 10 200 delete tap: openvpn --rmtun --dev tap0 - ARP request/reply OK - TFTP request OK - need to be tested with TFTP server. - need clean up
2015-03-09 13:30:21 +01:00
3e84c66ba9
vivado: permit resources without pins
...
This is required if the LOC is done by another, external constraints set,
as in the case of the Zynq Processing System Instance.
2015-03-09 13:30:19 +01:00
e60a97534b
mibuild/sim: able to visualize arp requests with wireshark
...
now need to find why that is not responding...
2015-03-06 20:16:30 +01:00
a64acdfa65
mibuild/sim: able to send ethernet frame from sim to server.py
2015-03-06 12:49:56 +01:00
0029b87628
mibuild/sim: add ethernet pins to verilor.py
2015-03-06 12:20:17 +01:00
658d4d4c49
platforms/sim: add ethernet pins
2015-03-06 10:20:26 +01:00
7b00141a0c
genlib/cordic: fix typos
2015-03-06 00:47:23 +01:00
06f3c46e35
genlib/misc: fix missing *args in Counter
2015-03-04 23:49:15 +01:00
3d7f9fd685
mibuild/sim/server_tb: use SERIAL_SINK_ACK
2015-03-04 00:55:35 +01:00
2d6fbd7902
mibuild/sim: use /tmp/simsocket sockaddr for server
2015-03-03 22:52:28 +01:00
f4b060f6fe
mibuild/sim: avoid updating end at each cycle (simulation speedup)
2015-03-03 18:01:14 +01:00
5ec26a49c3
mibuild/sim: simplify console_tb with sim struct
2015-03-03 17:57:58 +01:00
991572f4fe
mibuild/sim: create server.py and server_tb (Proof of concept OK with flterm)
...
Using a server allow us to create a virtual UART (and ethernet TAP in the future).
1) start the server
2) start flterm on the virtual serial port created by the server
3) run the simulation
This will enable us to do serialboot and netboot in simulation.
This will also enable prototyping ethernet for ARTIQ in simulation.
2015-03-03 17:38:22 +01:00
f154c2e7ec
xilinx/programmer/vivado: fix Linux support
2015-03-03 02:06:39 +00:00
154ad54a8e
platforms/kc705: fix imports
2015-03-03 02:03:14 +00:00
a56fce045b
Merge branch 'master' of http://github.com/m-labs/migen
2015-03-02 23:24:48 +01:00
29c5bb8bcd
mibuild/sim/verilator: remove verilator_root, use -Wno-fatal and add verbose option (verbose disabled by default)
2015-03-02 23:23:23 +01:00
36f4b68dd8
mibuild/sim: style fixes
2015-03-02 21:56:20 +00:00
7d68ecbd86
move dma_lasmi to MiSoC
2015-03-02 08:23:02 +01:00
58290f3c43
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
2015-03-01 22:04:20 +01:00
382ca374c3
mibuild: initial Verilator support
2015-03-01 18:27:46 +01:00
8f81ae6826
genlib/misc: add FlipFlop, Counter, Timeout
2015-03-01 16:33:46 +01:00
961b4bfb4c
platforms/pipistrello: remove unconnected SDRAM pins
2015-02-28 16:20:44 -07:00
03431ece9f
pipistrello: fix ddram dqs, cleanup constraints, add pullup/downs
2015-02-28 16:16:47 -07:00
75290aa0f3
pipistrello: switch back to xc3sprog and fast (papilio) speed
2015-02-28 16:16:47 -07:00
eb8ba145de
kx705: add programmer parameter
2015-02-28 23:34:57 +01:00
b53e2b0d6e
fix xilinx/programmer with Vivado
2015-02-28 19:33:20 +01:00
87d8ff2de7
xilinx/programmer: add source of vivado's settings (need to be tested on a linux machine)
2015-02-28 03:38:47 +01:00
e82531cdf8
move dfi/lasmibus/wishbone2lasmi to MiSoC sdram
2015-02-27 16:54:22 +01:00
225a2d4704
report cachesize in wishbone2lasmi
2015-02-27 14:12:13 +01:00
54a8a52e90
xilinx/programmer: add partial flash_bitstream for vivado (can flash full bitstream, need to be adapted to flash part of the flash (bios, ...))
2015-02-27 09:05:23 +01:00
2b0937153d
xilinx/programmer: fix xc3sprog (GenericProgrammer)
2015-02-26 21:36:15 -07:00
8de5b947bd
pipistrello: use fpgaprog
2015-02-26 21:34:02 -07:00
ca52aa5b8c
add fpgaprog programmer
2015-02-26 21:33:49 -07:00
Sebastien Bourdeauducq
Florent Kermarrec
Robert Jordens