Florent Kermarrec
|
58edd7632c
|
compiles but untested
|
2013-02-28 00:32:42 +01:00 |
Sebastien Bourdeauducq
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c10622f5e2
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fhdl/verilog: insert reset before listing signals
|
2013-02-27 18:10:04 +01:00 |
|
Florent Kermarrec
|
5accd48a17
|
doc: update
|
2013-02-26 23:45:01 +01:00 |
|
Florent Kermarrec
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87336128a3
|
sim: update
|
2013-02-26 23:25:10 +01:00 |
|
Florent Kermarrec
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ae900c9c16
|
examples: use miscope.bridges
|
2013-02-26 23:20:29 +01:00 |
|
Florent Kermarrec
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5fc89f0c71
|
move spi2csr to briges/spi2csr
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2013-02-26 23:17:34 +01:00 |
|
Florent Kermarrec
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f823d06cf1
|
examples: update & simplify
|
2013-02-26 23:14:09 +01:00 |
|
Florent Kermarrec
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b3ae31ee2f
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examples/../top: update
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2013-02-26 23:00:37 +01:00 |
|
Sebastien Bourdeauducq
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d2cbc70190
|
bank/description: memprefix
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2013-02-25 23:14:15 +01:00 |
|
Sebastien Bourdeauducq
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a81781f589
|
fhdl/specials: allow setting memory name
|
2013-02-25 23:14:03 +01:00 |
|
Sebastien Bourdeauducq
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425de02f42
|
uio/ioo: fix specials
|
2013-02-25 23:13:38 +01:00 |
|
Sebastien Bourdeauducq
|
356416fcdc
|
lm32: update
|
2013-02-24 17:42:28 +01:00 |
|
Sebastien Bourdeauducq
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70f4c74d46
|
m1crg: advance off-chip DDR clock phase
|
2013-02-24 17:41:56 +01:00 |
|
Sebastien Bourdeauducq
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5e6505b946
|
bios: print number of memory errors
|
2013-02-24 16:51:03 +01:00 |
|
Sebastien Bourdeauducq
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b854f1ad32
|
build: support optional MMU
|
2013-02-24 16:28:59 +01:00 |
|
Sebastien Bourdeauducq
|
43343b131f
|
lm32: use submodule
|
2013-02-24 15:57:19 +01:00 |
|
Sebastien Bourdeauducq
|
2b902fdcbd
|
xilinx_ise: import Instance
|
2013-02-24 15:36:56 +01:00 |
|
Sebastien Bourdeauducq
|
55ab01f928
|
fhdl/specials/Instance: _printintbool -> verilog_printexpr
|
2013-02-24 13:08:01 +01:00 |
|
Sebastien Bourdeauducq
|
0caac2246d
|
Use new 'specials' API
|
2013-02-24 13:07:25 +01:00 |
|
Sebastien Bourdeauducq
|
a22ada36d7
|
corelogic -> genlib
|
2013-02-24 12:31:00 +01:00 |
|
Sebastien Bourdeauducq
|
d60ab1d215
|
Use new 'specials' API
|
2013-02-24 12:21:01 +01:00 |
|
Sebastien Bourdeauducq
|
56ae0f0714
|
xilinx_ise: disable SRL extraction on synchronizers
|
2013-02-23 19:43:12 +01:00 |
|
Sebastien Bourdeauducq
|
ef833422c7
|
generic_platform/get_verilog: pass additional args to verilog.convert
|
2013-02-23 19:42:29 +01:00 |
|
Sebastien Bourdeauducq
|
0321513726
|
corelogic -> genlib
|
2013-02-23 19:37:27 +01:00 |
|
Sebastien Bourdeauducq
|
c2d54f481f
|
examples/psync: cleanup
|
2013-02-23 19:14:31 +01:00 |
|
Sebastien Bourdeauducq
|
6abac5907b
|
examples/basic/psync: demonstrate the new features
|
2013-02-23 19:04:11 +01:00 |
|
Sebastien Bourdeauducq
|
a878db1e3c
|
genlib: clock domain crossing elements
|
2013-02-23 19:03:35 +01:00 |
|
Sebastien Bourdeauducq
|
7c4e6c35e5
|
fhdl/verilog: support special lowering and overrides
|
2013-02-23 19:03:16 +01:00 |
|
Sebastien Bourdeauducq
|
3a591c358c
|
examples/fir: better filter
|
2013-02-22 23:19:56 +01:00 |
|
Sebastien Bourdeauducq
|
f9acee4e68
|
corelogic -> genlib
|
2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
|
38664d6e16
|
fhdl: inline synthesis directive support
|
2013-02-22 19:10:02 +01:00 |
|
Sebastien Bourdeauducq
|
587f50cf90
|
doc: new 'specials' API
|
2013-02-22 18:12:42 +01:00 |
|
Sebastien Bourdeauducq
|
49cfba50fa
|
New 'specials' API
|
2013-02-22 17:56:35 +01:00 |
|
Florent Kermarrec
|
e95e8b03b7
|
- reworking WIP
|
2013-02-22 16:40:49 +01:00 |
|
Sebastien Bourdeauducq
|
44ae20d3c4
|
generic_platform: prefix subsignals
|
2013-02-20 18:27:04 +01:00 |
|
Sebastien Bourdeauducq
|
e82ea19cdc
|
doc: tristates
|
2013-02-19 17:52:57 +01:00 |
|
Sebastien Bourdeauducq
|
1b18194b1d
|
fhdl: TSTriple
|
2013-02-19 17:26:02 +01:00 |
|
Sebastien Bourdeauducq
|
dfec152422
|
Build FPG file
|
2013-02-19 13:27:43 +01:00 |
|
Sebastien Bourdeauducq
|
3f22930b1f
|
tools: add byteswap
|
2013-02-19 13:22:35 +01:00 |
|
Sebastien Bourdeauducq
|
07120e3c3e
|
bios: use puts for long string
|
2013-02-17 16:21:25 +01:00 |
|
Sebastien Bourdeauducq
|
8247f3a154
|
bios: add build date to banner
|
2013-02-17 14:29:11 +01:00 |
|
Sebastien Bourdeauducq
|
b135d87ca2
|
Makefile: correct bitstream filename
|
2013-02-17 00:12:15 +01:00 |
|
Sebastien Bourdeauducq
|
20003f0ada
|
software: go back to GCC
|
2013-02-16 23:41:42 +01:00 |
|
Sebastien Bourdeauducq
|
244cfbc7a2
|
add README, LICENSE and gitignore
|
2013-02-15 19:56:44 +01:00 |
|
Sebastien Bourdeauducq
|
c56c916129
|
load.jtag: remove CFG_OUT/CFG_IN instructions
|
2013-02-15 19:39:54 +01:00 |
|
Sebastien Bourdeauducq
|
dc93a231c6
|
fhdl: tristate support
|
2013-02-15 00:17:24 +01:00 |
|
Sebastien Bourdeauducq
|
38c3566717
|
generic_platform: add name
|
2013-02-14 20:02:35 +01:00 |
|
Sebastien Bourdeauducq
|
7ad2f7081b
|
m1crg: fix signal names
|
2013-02-13 23:59:35 +01:00 |
|
Sebastien Bourdeauducq
|
ed4d65f2be
|
generic_platform: fix IO signal set when using existing record objects
|
2013-02-13 23:29:33 +01:00 |
|
Sebastien Bourdeauducq
|
feec035cc8
|
generic_platform: get absolute path for added sources
|
2013-02-12 19:16:00 +01:00 |