Sebastien Bourdeauducq
71e3bba228
dvisampler/decoding: hold C when DE=1
2013-05-05 11:51:48 +02:00
Sebastien Bourdeauducq
4259699d78
dvisampler: add RawDVISampler
2013-05-04 20:40:21 +02:00
Sebastien Bourdeauducq
63073319b0
dvisampler/datacapture: swap bit pairs
2013-05-04 20:38:50 +02:00
Sebastien Bourdeauducq
8222ee7f46
framebuffer: use DMA controller from Migen
2013-04-30 18:55:35 +02:00
Sebastien Bourdeauducq
43ac5c8471
Remove undriven reset signals
2013-04-25 20:19:49 +02:00
Sebastien Bourdeauducq
4ff1175dcf
Use the Migen asynchronous FIFO
2013-04-25 19:43:26 +02:00
Sebastien Bourdeauducq
117b3b8ec7
adc: double-register asynchronous inputs
2013-04-19 12:32:12 +02:00
Werner Almesberger
0dca526a85
milkymist/adc/__init__.py: CounterADC - simple counter-based ADC
...
This is a revised version of the counter-based ADC.
2013-04-19 12:29:17 +02:00
Sebastien Bourdeauducq
b018fcedc4
dvisampler/chansync: set synced to 0 when control tokens do not arrive at the same time
2013-04-16 22:21:03 +02:00
Sebastien Bourdeauducq
0d21711c1b
dvisampler/chansync: use Record.raw_bits()
2013-04-14 17:06:29 +02:00
Sebastien Bourdeauducq
8914969760
dvisampler/clocking: insert DCM_CLKGEN before PLL
2013-04-14 16:53:19 +02:00
Werner Almesberger
7a6e56492c
edid.py: sample SCL only every 64 clock cycles, to avoid bouncing
...
Possibly due to SCL rising fairly slowly (in the 0.5-1 us range),
bouncing has been observed while crossing the "forbidden" region
between Vil(max) and Vih(min).
By lowering the sample rate from once per system clock to once
every 64 clock cycles, we make sure we sample at most once during
the bounce interval and thus never see a false edge. (Although we
may see a rising edge one sample time late, which is perfectly
harmless.)
2013-04-12 22:48:46 +02:00
Sebastien Bourdeauducq
950d3a4469
framebuffer: use new flow API
2013-04-10 21:34:15 +02:00
Sebastien Bourdeauducq
3be20f6ae4
dfii: adapt to new Record API
2013-04-02 00:15:42 +02:00
Sebastien Bourdeauducq
4f4f260e76
Convert to new CSR API
2013-03-30 17:28:15 +01:00
Sebastien Bourdeauducq
caa19f9ab2
framebuffer: larger counters
2013-03-29 17:15:11 +01:00
Sebastien Bourdeauducq
854c0461b4
framebuffer: process two pixels per system clock cycle
2013-03-28 20:46:16 +01:00
Sebastien Bourdeauducq
8fd092ca12
crg: support VGA pixel clock reprogramming
2013-03-28 19:07:17 +01:00
Sebastien Bourdeauducq
1e860c7472
Use new Mibuild generic_platform API
2013-03-26 17:57:17 +01:00
Sebastien Bourdeauducq
1045d64e6e
framebuffer: RGBA -> ARGB
2013-03-25 18:32:25 +01:00
Sebastien Bourdeauducq
8ee6dab4f9
fb: better ordering of pixels within ASMI words
2013-03-25 15:56:54 +01:00
Sebastien Bourdeauducq
1333367de8
dvisampler: add resolution detection
2013-03-24 00:45:29 +01:00
Sebastien Bourdeauducq
ee5bfd4d3d
dvisampler/charsync: report position
2013-03-24 00:44:50 +01:00
Sebastien Bourdeauducq
99f9ffa7e8
dvisampler/decoding: set C to 0 during data
2013-03-24 00:44:19 +01:00
Sebastien Bourdeauducq
fb9a2788e8
dvisampler/charsync: fix found_control signal
2013-03-24 00:43:22 +01:00
Sebastien Bourdeauducq
e06585d9fe
dvisampler: clean up EDID data
2013-03-23 13:48:40 +01:00
Sebastien Bourdeauducq
34b8388b45
dvisampler: decode before channel sync
2013-03-22 23:49:25 +01:00
Sebastien Bourdeauducq
037625886d
dvisampler: decoding
2013-03-22 21:28:17 +01:00
Sebastien Bourdeauducq
d65941d6cc
dvisampler: channel synchronization
2013-03-22 18:37:10 +01:00
Sebastien Bourdeauducq
515cdb2bd8
dvisampler: character synchronization
2013-03-21 22:56:13 +01:00
Sebastien Bourdeauducq
7c4ca4fd66
dvisampler/datacapture: deserialize to 10 bits
2013-03-21 19:06:15 +01:00
Sebastien Bourdeauducq
fa2331e084
dvisampler/clocking: generate pix reset
2013-03-21 19:02:04 +01:00
Sebastien Bourdeauducq
0a14c3714b
dvisampler: software controlled phase detector
2013-03-21 00:46:29 +01:00
Sebastien Bourdeauducq
28cb97068c
dvisampler/clocking: proper pix5x reset synchronization
2013-03-18 20:31:59 +01:00
Sebastien Bourdeauducq
5126f616fb
dvisampler: use pix5x as IODELAY clock
2013-03-18 19:03:17 +01:00
Sebastien Bourdeauducq
48aae9bee5
Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
2013-03-18 17:44:01 +01:00
Sebastien Bourdeauducq
74cc045ee1
dvisampler/datacapture: connect IODELAY IOCLK0
2013-03-17 17:42:22 +01:00
Sebastien Bourdeauducq
621526fb7d
dvisampler/datacapture: fix tap counter reg
2013-03-17 17:36:49 +01:00
Sebastien Bourdeauducq
3a0cf278fd
dvisampler: fixes
2013-03-17 15:41:50 +01:00
Sebastien Bourdeauducq
9f02ced39e
dvisampler: add clocking and phase detector
2013-03-17 14:43:10 +01:00
Sebastien Bourdeauducq
0168f83523
MultiReg: remove idomain
2013-03-15 19:51:29 +01:00
Sebastien Bourdeauducq
b2173bba9f
Use new ClockDomain API
2013-03-15 19:17:05 +01:00
Sebastien Bourdeauducq
e99bafe52b
dvisampler: add core, EDID support
2013-03-13 19:56:26 +01:00
Sebastien Bourdeauducq
a23df42a7a
Use automatic register naming
2013-03-12 15:47:54 +01:00
Sebastien Bourdeauducq
a9b723568a
Use new module, autoreg and eventmanager Migen APIs
2013-03-10 19:32:38 +01:00
Sebastien Bourdeauducq
0caac2246d
Use new 'specials' API
2013-02-24 13:07:25 +01:00
Sebastien Bourdeauducq
a22ada36d7
corelogic -> genlib
2013-02-24 12:31:00 +01:00
Sebastien Bourdeauducq
5649e88a90
Use Mibuild
2013-02-11 18:23:06 +01:00
Sebastien Bourdeauducq
51f4f920a2
Do not use super()
2012-12-18 14:55:58 +01:00
Sebastien Bourdeauducq
c44ff8941c
Move Token
2012-12-14 15:54:16 +01:00