f6624b34f0
migen/actorlib/spi: apply missing CSR renaming
2015-05-13 10:17:31 +02:00
1cbc468bda
migen/actorlib/packet: add Packetizer and Depacketizer
2015-04-28 18:44:05 +02:00
3ce5ff3722
migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer)
2015-04-27 15:14:38 +02:00
f976b1916a
migen/actorlib/misc: add BufferizeEndpoints
...
BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
2015-04-27 15:12:01 +02:00
5f225c0475
global: pep8 (E225)
2015-04-13 21:11:13 +02:00
1051878f4c
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
17e5249be0
global: pep8 (replace tabs with spaces)
2015-04-13 20:07:07 +02:00
ce0ff1e341
remove use of _r prefix on CSRs
2015-04-02 12:15:56 +02:00
7d68ecbd86
move dma_lasmi to MiSoC
2015-03-02 08:23:02 +01:00
58290f3c43
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
2015-03-01 22:04:20 +01:00
452c60e0c3
endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations)
2015-02-14 03:10:56 -08:00
319465445d
actorlib/structuring: fix eop generation in Pack
2015-02-14 03:07:18 -08:00
c7eba8f4c4
remove crc since each crc is specific. It's probably better to adapt code for each case.
2015-02-14 03:01:12 -08:00
037ea05b1e
crc: modify CRCChecker to remove CRC and clean up
2014-12-21 17:24:52 +08:00
eb47f458dd
flow: endpoint description structure with packetized parameter
2014-11-20 22:31:56 -08:00
f5fc4b365f
actorlib/fifo: add buffered parameter
2014-11-20 18:46:54 -08:00
f847faf004
actorlib/fifo: fix no-op assignment due to .payload omission
2014-11-14 21:25:19 +01:00
dcedc4e6a5
actorlib/structuring/Pipeline: make 'busy' a signal
2014-11-01 21:48:02 +08:00
33c3a927c2
actorlib/structuring: add Pipeline
...
Pipeline enables easy cascading of dataflow modules.
DataFlowGraph can eventually use it to implement the
add_pipeline method to avoid duplicating things.
2014-11-01 21:47:00 +08:00
8db549a23d
actorlib/structuring: add Converter
...
Converter enables easy conversions of data width on dataflows.
It handles the 3 possibles cases:
- downconverter
- upconverter
- direct connection when data width are identical.
2014-11-01 21:43:52 +08:00
bd1d456f5d
flow/actor, actorlib/structuring: add packet support
2014-11-01 21:22:46 +08:00
fcf2f7517c
crc: generate error asynchronously to avoid stalling the flow and simplify
2014-11-01 21:21:46 +08:00
37031e3a2f
DMAWriteController: fix Demultiplexer layout
2014-10-20 23:58:16 +08:00
07c33279c2
use new direct access on endpoints
2014-10-20 23:12:16 +08:00
dbaeaf7833
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
e03091e7e2
add generic CRCEngine, CRC32, CRCInserter and CRCChecker
...
CRCEngine implements a generic and optimized CRC LFSR. It will enable generation of CRC generators and checkers.
CRC32 is an implementation of IEEE 802.3 CRC using the CRCEngine.
CRC32Inserter and CRC32Checker have been tested on an ethernet MAC.
2014-09-26 11:42:10 +08:00
967b73bef3
actorlib/structuring: add reverse parameter to Unpack and Pack
2014-09-22 23:41:40 +08:00
325ffdc6c6
actorlib/spi: remove unneeded import
2014-09-08 18:48:54 +08:00
c1e12c3346
actorlib/spi: remove EventManager from DMAController
2014-09-08 11:34:21 +08:00
2ab939e69d
fix SimActor TB terminations
2014-01-28 00:03:56 +01:00
63c1d7e4b7
New simulation API
2014-01-26 22:19:43 +01:00
c3aad93753
actorlib/spi/DMAWriteController: make ack_when_inactive a keyword-only arg
2013-11-02 23:21:05 +01:00
e0e99ec385
actorlib/spi: add ack_when_inactive parameter to DMA Write Controller
...
In some cases we don't want to stall the input pipeline when the DMA is inactive, setting ack_when_inactive to True will enable acknowledge of data when the DMA is inactive.
2013-11-02 23:16:05 +01:00
91422788ef
actorlib/fifo: do not duplicate safe write logic
2013-09-04 17:33:53 +02:00
523565be63
actorlib/spi/DMAController: use EventSourceProcess
2013-09-04 17:29:42 +02:00
b6eb97e49f
actorlib/spi: add optional irq generation on DMAController
2013-09-04 17:27:57 +02:00
1209ec17f6
actorlib/fifo: rewrite
...
* use classes for less code duplication
* the idea of decorator is to avoid passing common parameters (e.g. clock domain names) in module constructors, so remove those parameters
* style
2013-09-04 17:22:50 +02:00
71b14ac873
actorlib: add fifo
2013-09-04 17:15:22 +02:00
e05f520cdf
actorlib/spi: remove unused function
2013-07-27 15:36:42 +02:00
5b36f688ea
Remove ASMI
2013-07-16 18:50:50 +02:00
65a0b12812
actorlib/spi/DMAController: export length/storage/trigger
2013-07-13 17:13:15 +02:00
6595b9a111
actorlib/spi/SingleGenerator: export CSRs
2013-07-13 17:12:51 +02:00
6aa1e0c199
actorlib/spi/DMAWriteController: len -> flen
2013-07-11 19:22:56 +02:00
af6ef0a3b4
dma_lasmi/Writer: fix default FIFO depth
2013-07-07 20:01:55 +02:00
fa8112c3f5
dma_lasmi/Reader: handle ack=1 when stb=0
2013-07-07 18:57:05 +02:00
d0caa738bd
FSM: new API
2013-06-25 22:17:39 +02:00
d6f7b4cee6
lasmi: separate request and data ack to support bankmachine FIFOs (buggy/incomplete)
2013-06-17 23:36:03 +02:00
fe54c68762
lasmi: fix minor problems
2013-06-10 22:49:33 +02:00
3a284b9c1e
actorlib: LASMI DMA (untested)
2013-06-10 22:29:39 +02:00
bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
Florent Kermarrec
Sebastien Bourdeauducq
Jannis Harder
Sebastien Bourdeauducq