Commit Graph

6603 Commits

Author SHA1 Message Date
Florent Kermarrec 7513460572 integration/soc/add_pcie: add with_msi parameter to allow disabling MSI when not required.
When just doing a PCIe to Wishbone Bridge (PCIeBone), DMAs and MSI are not required, with_msi
will allow disabling MSI when set to False.
2021-02-19 11:35:49 +01:00
Florent Kermarrec d4edc132c1 tools/remote/comm_pcie: fix typo. 2021-02-19 10:33:04 +01:00
Florent Kermarrec b47160c74e tools/litex_term: replace CrossoverUART with BridgeUART for more genericity, rework bridge/jtag args.
The CrossoverUART was in fact a particular UART connected to a second UART. Being able
to have access to multiple UARTs over a Bridge can be useful for several purposes, ex:

SoC0 --> UART0 +            JTAGBone                   + litex_term bridge --bridge-name=UART0
SoC1 --> UART1 +--> SoC --> UARTBone  --> LiteX-Server + litex_term bridge --bridge-name=UART1
SoC2 --> UART2 +            EtherBone                  + litex_term bridge --bridge-name=UART2
2021-02-18 18:02:05 +01:00
Florent Kermarrec 6ac410a462 cores/uart/UARTCrossover: increase rx_fifo_depth to allow speeding up litex_term. 2021-02-18 17:55:53 +01:00
Florent Kermarrec fc83a9281a interconnect/csr: remove address wrapping within a CSRBank.
To minimize logic, decoding inside a CSRBank to limited to the CSRs inside
the bank and could wraps since partially decoded:

For example, accessing SoCController on addresses still on the CSRBank defined
for real CSRs produced:

litex> mem_read 0x82000000 128
Memory dump:
0x82000000  00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00  ....xV4.........
0x82000010  00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00  ....xV4.........
0x82000020  00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00  ....xV4.........
0x82000030  00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00  ....xV4.........
0x82000040  00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00  ....xV4.........
0x82000050  00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00  ....xV4.........
0x82000060  00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00  ....xV4.........
0x82000070  00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00  ....xV4.........

This is generally not an issue on most of the systems, but it could confuse user
or produce un-wanted behaviour when bus data-width converter are used.

With this change, the address is fully decoded, which removes the address wrapping:

litex> mem_read 0x82000000 128
Memory dump:
0x82000000  00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00  ....xV4.........
0x82000010  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
0x82000020  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
0x82000030  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
0x82000040  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
0x82000050  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
0x82000060  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
0x82000070  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................

Resource usage increase seems minimal.
2021-02-18 14:44:50 +01:00
Florent Kermarrec 12bdf43958 soc/cores/ecc: cosmetic cleanups. 2021-02-18 10:00:27 +01:00
Florent Kermarrec 7ce5aef428 soc/cores/led: add add_pwm method to allow adjusting brightness dynamically (or not).
LedChaser without PWM:

self.submodules.leds = LedChaser(
    pads         = platform.request_all("user_led"),
    sys_clk_freq = sys_clk_freq)
self.add_csr("leds")

Add PWM to it (with default values: 50% duty cycle):
self.leds.add_pwm()

Add PWM with custom default values (25% duty cycle here):
self.leds.add_pwm(default_width=128, default_period=1024)

Then adjust brightness dynamically from the BIOS or your software:

$cat csr.csv:
csr_register,leds_out,0x82003000,1,rw
csr_register,leds_pwm_enable,0x82003004,1,rw
csr_register,leds_pwm_width,0x82003008,1,rw
csr_register,leds_pwm_period,0x8200300c,1,rw

Set PWM to 0%:
$mem_write 0x82003008 0

Set PWM to 25%:
$mem_write 0x82003008 256

Set PWM to 50%:
$mem_write 0x82003008 512

Set PWM to 75%:
$mem_write 0x82003008 768

Set PWM to 100%:
$mem_write 0x82003008 1024

You can also only use default values and disable CSR is dynamic configuration is not
required (with_csr=False) or adjust PWM period if want to use a specific PWM period
in your system.
2021-02-18 09:47:30 +01:00
Florent Kermarrec fc282b3084 soc/cores/pwm: add configurable default enable/width/period values. 2021-02-18 09:39:18 +01:00
Florent Kermarrec 908e72e65b cores/uart: rewrite RS232PHYTX/RX (with FSM and comments) and optimize resource usage (~100LCs). 2021-02-17 15:04:14 +01:00
enjoy-digital 7c7f540488
Merge pull request #821 from jersey99/master
build/xilinx/vivado.py: Allow a tcl script to be added as ip
2021-02-17 08:12:09 +01:00
Florent Kermarrec 82c1f5dccb litex_setup/ibex: add pythondata-misc-opentitan to litex_setup and use it for Ibex CPU. 2021-02-17 08:07:07 +01:00
Florent Kermarrec 285bb96278 cores/uart/RS232PHY: add with_dynamic_baudrate parameter and disable it by default.
Dynamic baudrate is rarely used and enabling it has a non negligeable cost (~100LCs).
2021-02-16 20:00:43 +01:00
Florent Kermarrec 9a8a8c0fe5 software/liblitedram: remove SDRAM_PHY_WRITE_LEVELING_REINIT no longer required on Ultrascale(+). 2021-02-16 16:26:34 +01:00
Vamsi Vytla 385dec8560 Merge remote-tracking branch 'upstream/master' 2021-02-15 09:29:47 -08:00
Vamsi Vytla 1fde282291 build/xilinx/vivado.py: Allow a tcl script to be added as ip. These tcl scripts tend to generate .xci's on the fly. The tcl script can be looked up in the vivado console as the ip is generated 2021-02-15 09:29:00 -08:00
enjoy-digital 5291a646d2
Merge pull request #820 from gsomlo/gls-sdcard-fixes
fixes for boot and (single-block, cmd17-only) Linux driver
2021-02-15 15:44:18 +01:00
Gabriel Somlo 927fd675bc sdclk: additional halving to prevent clock going "too fast"
When the system/bus clock frequency is an exact power-of-2 multiple of
the desired sdcard frequency, we can drive the latter at the "maximum"
speed via the "perfect" divider. That sometimes turns out too fast, so
in order to be conservative, we double the divider, thus halving the
resulting sdclock.
2021-02-15 09:24:02 -05:00
Gabriel Somlo b03f46ffec soc: increase sdcard data/cmd timeout (from default 10e-3)
This allows the Linux driver in single-block mode (cmd17-only) to
operate solidly, without running into timeouts from LiteSDCard FSMs.

FIXME: multi-block (cmd18) transfers still time out, so revisit this
after some additional debugging.
2021-02-15 09:23:52 -05:00
enjoy-digital 07dd680a3e
Merge pull request #818 from tcal-x/vexLiteMul
Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions.
2021-02-15 15:02:47 +01:00
Florent Kermarrec 510bda4c99 cores/cpu: add initial lowRISC's Ibex support (without interrupts).
Working in simulation and on hardware: litex_sim --cpu-type=ibex, ./target.py --cpu-type=ibex.

This is currently doing a git clone of ibex and opentitan repositories but we'll
create a pythondata-cpu-ibex package in the future.

litex_sim --cpu-type=ibex:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb 15 2021 11:57:50
 BIOS CRC passed (e7517f7b)

 Migen git sha1: 7014bdc
 LiteX git sha1: ead12df2

--=============== SoC ==================--
CPU:		Ibex @ 1MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		32KiB
SRAM:		8KiB
MAIN-RAM:	262144KiB

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--
2021-02-15 12:02:25 +01:00
Tim Callahan 5cb467cae3 Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions.
Signed-off-by: Tim Callahan <tcal@google.com>
2021-02-14 14:16:14 -08:00
Florent Kermarrec ead12df21b soc/cores/gpio: review/simplify #810.
Use irqs dict and "rise", "fall" strings instead of Enums:

Ex: pads=Signal(8), irqs={}                    : 8-bit Input, No IRQ.
    pads=Signal(8), irqs={0: "rise", 7: "fall"}: 8-bit Input, rising IRQ on 0, falling IRQ on 1.

Also simplify the logic.
2021-02-12 16:21:01 +01:00
enjoy-digital 89454d2df3
Merge pull request #810 from antmicro/gpio_interrupts
Add support for interrupts on GPIOIn
2021-02-12 15:51:25 +01:00
enjoy-digital 159155b3e6
Merge pull request #816 from geertu/software-demo-Drop-bogus-the-in-README
software/demo: Drop bogus "the" in README
2021-02-12 15:32:50 +01:00
Geert Uytterhoeven d91262e85c software/demo: Drop bogus "the" in README
Fixes: e7e28f2438 ("Change wording of demo README")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-12 15:15:55 +01:00
enjoy-digital 0366a03c87
Merge pull request #813 from antmicro/jboc/lpddr4
software/bios: add option to disable BIOS prompt
2021-02-12 14:08:34 +01:00
enjoy-digital 25244629e9
Merge pull request #815 from nickoe/reword_demo_readme
Change wording of demo README
2021-02-12 13:57:19 +01:00
Florent Kermarrec 3b00a7c4fe README: Add link to the Wiki in the Welcome section. 2021-02-12 13:40:11 +01:00
Nick Østergaard e7e28f2438 Change wording of demo README
Change wording of demo README to make it more clear what the process is
and how things related.  This should help the newcomer and it still
usefull for the triained.

Change the command example to be more copy paste friendly.

Fixes #814
2021-02-11 21:35:02 +01:00
Jędrzej Boczar 5f1edccd2e software/bios: add option to disable BIOS prompt 2021-02-11 10:49:45 +01:00
Florent Kermarrec 041aa9bf6f soc/cores/clock/xilinx_us/USIDELAYCTRL: make sure sys clock domain is reseted when reference clock domain is reseted. 2021-02-09 19:06:49 +01:00
Florent Kermarrec 126dd267d6 soc/interconnect/axi/AXIInterface: add optional tkeep. 2021-02-09 16:27:48 +01:00
Robert Szczepanski 15b3d932a4 gpio: add support for interrupts on GPIOIn 2021-02-09 15:29:31 +01:00
enjoy-digital 018094abb2
Merge pull request #809 from stffrdhrn/mor1kx-smp
cpu/mor1kx: Add initial SMP support to cpu core
2021-02-09 09:54:49 +01:00
enjoy-digital 95b310ee0f
Merge pull request #807 from antmicro/revert-bitstream-device-changes
build/xilinx/symbiflow: fix bitstream_device select
2021-02-09 09:26:48 +01:00
enjoy-digital b9bc1d8457
Merge pull request #806 from geertu/bios-improvements
Bios improvements
2021-02-09 09:24:35 +01:00
Stafford Horne 2f2b047f2e cpu/mor1kx: Add initial SMP support to cpu core
In order for mor1kx to run an SMP kernel shadow registers must be
enabled.  This patch adds two new variants:

 - linux+smp - basic linux + smp support
 - linux+smp+fpu - linux with FPU and smp support
2021-02-09 07:06:07 +09:00
Jan Kowalewski ad760d491c build/xilinx/symbiflow: fix bitstream_device select
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-08 15:38:30 +01:00
Geert Uytterhoeven 84e5130ac5 software/bios/console: Call putsnonl() from puts()
puts() and putsnonl() are very similar, and can share code.
Reduce code size by making the former call the latter.

Impact for a RISC-V build:

    $ size console.o.orig console.o
       text	   data	    bss	    dec	    hex	filename
	868	      0	     12	    880	    370	console.o.orig
	832	      0	     12	    844	    34c	console.o

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-08 14:05:31 +01:00
Geert Uytterhoeven 8e4202ced1 software/bios/readline: Fix warnings if char is signed
When building with --cpu-type=mor1kx:

    litex/soc/software/bios/readline.c: In function 'readline':
    litex/soc/software/bios/readline.c:271:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
      271 |   case KEY_END:
	  |   ^~~~
    litex/soc/software/bios/readline.c:297:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
      297 |   case KEY_DEL:
	  |   ^~~~
    litex/soc/software/bios/readline.c:281:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
      281 |   case DEL:
	  |   ^~~~

The C standard does not specify the signedness of "char", hence this
depends on the implementation.  On e.g. RISC-V, "char" is unsigned, but
on OpenRISC, it is signed.

Fix this by making the "ichar" variable explicitly unsigned.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-08 14:05:31 +01:00
Florent Kermarrec 5430c1455e software/demo: add support for absolute/relative --build-path and simplify comment. 2021-02-08 10:29:26 +01:00
enjoy-digital 876ee69e69
Merge pull request #803 from hansfbaier/master
demo: more helpful usage message / support Altera JTAG in litex_term
2021-02-08 10:18:58 +01:00
Florent Kermarrec b485829ec4 MANIFEST.in: update. 2021-02-08 10:11:10 +01:00
Hans Baier 7dae0aa09b litex_term: support Intel/Altera nios2-terminal 2021-02-08 11:42:37 +07:00
Hans Baier 6f63fc104e demo: more helpful usage message 2021-02-06 07:15:12 +07:00
Florent Kermarrec 5cb9f487a2 tools/litex_server: remove JTAGUART's binary_mode parameter (we are now only supporting binary_mode). 2021-02-05 12:38:20 +01:00
Florent Kermarrec 468b916a4f tools/litex_term: add --jtag-config parameter to select OpenOCD JTAG configuration file. 2021-02-05 09:43:32 +01:00
Florent Kermarrec 4f15be746c tools/litex_term: always use binary mode (for jtag_uart and jtagbone) and remove parameter.
Fix jtag_uart regression and allow serialboot.
2021-02-05 09:40:21 +01:00
enjoy-digital 92f4cd1423
Merge pull request #799 from antmicro/add_xc7a200t_to_symbiflow
build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain
2021-02-04 16:41:45 +01:00
enjoy-digital 0006efe6ea
Merge pull request #800 from geertu/doc-sphinx-v1-fix
doc: Fix doc build with Sphinx v1.x
2021-02-04 12:24:49 +01:00