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Author SHA1 Message Date
Dolu1990
92ef330c12 cpu/Vexriscv-smp fix silent generation failure 2023-01-16 18:02:32 +01:00
Florent Kermarrec
88453716dc cpu/vexriscv_smp/core: Only raise error with FPU. 2023-01-16 12:59:14 +01:00
Florent Kermarrec
a4d5919a2a cpu/vexriscv_smp/core: Raise an error in do_finalize if no direct memory bus found and wishbone_memory is not set instead of forcing it. 
This could eventually be improved in the future but for now will prevent silent incorrect builds.
 2023-01-16 11:49:36 +01:00
Florent Kermarrec
a39e2c836a tools/litex_sim: Fix missing update in ram_init. 2023-01-16 11:12:24 +01:00
Florent Kermarrec
5760c5ba1e integration/soc/alloc_region: Fix alignment of Origin on Size (Thanks @sensille). 2023-01-16 09:20:43 +01:00
enjoy-digital
8b14e64906
Merge pull request #1566 from antmicro/msieron/sdram-read-spd-fix 
liblitedram/sdram_spd: fix invalid buffer index
 2023-01-12 16:51:20 +01:00
Michal Sieron
6a38e83ff6 liblitedram/sdram_spd: fix invalid buffer index 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-12 13:48:33 +01:00
enjoy-digital
63169aa5db
Merge pull request #1564 from antmicro/msieron/fix-write-leveling-for-x4 
software/liblitedram: fix write leveling for x4 modules
 2023-01-12 12:49:32 +01:00
Florent Kermarrec
f386f4a2a5 cores/pwm: Add reset signal to be able to synchronize PWM with an external signal. 2023-01-12 11:43:55 +01:00
Florent Kermarrec
461b48fbaa test/test_cpu: Disable microwatt test for now since seems broken (GHDL issue). 
Will need to be investigated:
https://github.com/enjoy-digital/litex/actions/runs/3900056883/jobs/6662146988

Command line:
ghdl --synth --out=verilog --std=08 --no-formal /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/wishbone_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/utils.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/common.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/nonrandom.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fetch1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cache_ram.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/plrufn.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/dcache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/icache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/insn_helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/predecode.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/control.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode2.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/register_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/crhelpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cr_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/ppc_fx_insns.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/logical.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/rotator.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/countbits.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/execute1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/loadstore1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/divider.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fpu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/pmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/writeback.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/mmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core_debug.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply-32s.vhdl /home/runner/work/litex/litex/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/wishbone_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/utils.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/common.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/nonrandom.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fetch1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cache_ram.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/plrufn.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/dcache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/icache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/insn_helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/predecode.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/control.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode2.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/register_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/crhelpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cr_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/ppc_fx_insns.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/logical.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/rotator.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/countbits.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/execute1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/loadstore1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/divider.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fpu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/pmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/writeback.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/mmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core_debug.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply-32s.vhdl /home/runner/work/litex/litex/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl -e microwatt_wrapper
Exception SYSTEM.ASSERTIONS.ASSERT_FAILURE raised
Exception information:
raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : elab-vhdl_annotations.adb:1401
Call stack traceback locations:
0x7fc79b8b0542 0x5631cf7cd3d0 0x5631cf7c8bf1 0x5631cf7c9219 0x5631cf7c93d2 0x5631cf7c977f 0x5631cf7ca0d3 0x5631cf7ca21a 0x5631cf7c9c41 0x5631cf7cbc0c 0x5631cf889270 0x5631cf97faf6 0x5631cf857fb0 0x5631cf988b5a 0x5631cf6d43d7 0x7fc79b432d8e 0x7fc79b432e3e 0x5631cf6d2f83 0xfffffffffffffffe
 2023-01-12 11:43:17 +01:00
enjoy-digital
803fb6323e
Merge pull request #1561 from roby2014/master 
Add Arch Linux setup support for RISC-V and OpenRISC toolchains
 2023-01-12 08:22:02 +01:00
awyxx
fa28d70e62 added powerpc via AUR repository 2023-01-11 23:48:17 +00:00
Michal Sieron
881bdbbbef software/liblitedram: fix write leveling for x4 modules 
When using x4 modules, their response makes up only half a byte.
We need to extract the nibble and then test it.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 21:21:00 +01:00
enjoy-digital
d67a7b13ae
Merge pull request #1563 from trabucayre/improve_LiteXArgumentParser 
Improve LiteXArgumentParser
 2023-01-11 19:15:58 +01:00
Gwenhael Goavec-Merou
d70049c2e1 build/parser: adding a fallback to search for a platform explicitly into litex-boards package when platform name isn't found 2023-01-11 18:33:48 +01:00
Gwenhael Goavec-Merou
35f4913588 build/parser: adding a method to search default value for an argument into ArgParse._actions 2023-01-11 18:31:31 +01:00
awyxx
2f2a1e8947 Removed debug print 2023-01-10 21:42:49 +00:00
awyxx
fec8bbe42c added arch linux support for riscv and openrisc toolchains 2023-01-10 21:41:35 +00:00
Michal Sieron
cc27e3d6c7 cmds/cmd_litedram: add sdram_hw_test command 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-10 13:01:00 +01:00
Michal Sieron
dbf030e4cf liblitedram/bist: add sdram_hw_test function 
It allows to perform a memtest (similar to `sdram_test`), but using DMAs
and bypassing system bus. This way, one can test ranges such above 4 GiB,
which was the limit with `sdram_test` due to address_width being limited
to 32 bits.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-10 13:01:00 +01:00
Michal Sieron
e7e1b16027 liblitedram/bist: small refactor of bist functions 
`SDRAM_TEST_DATA_BYTES` definition was incorrect as it treated size
specified in CSR subregisters as if it was a byte count.

Correct way to calculate that is to use definitions from `sdram_phy.h`.

```
#define SDRAM_TEST_DATA_BYTES (SDRAM_PHY_DFI_DATABITS / 8 * SDRAM_PHY_PHASES)
```

Also:
- extracted code to `sdram_bist_[write|read]` functions
- made global variables static
- fixed formatting

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-10 13:00:54 +01:00
Michal Sieron
eb688d3af7 tools/litex_sim: allow to enable BIST modules 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-10 12:36:18 +01:00
Florent Kermarrec
c834387965 soc/cores/hyperbus: Expose burst_timer to ease debug. 2023-01-10 11:09:45 +01:00
Florent Kermarrec
1f2a44516e soc/cores/dma/WishboneDMAReader: Add back endianness swap afer FIFO addition. 2023-01-10 10:51:13 +01:00
Florent Kermarrec
2d7cd7802c software/liblitedram Fix compilation when no SDRAM. 2023-01-10 10:17:10 +01:00
enjoy-digital
0a36ad1f6d
Merge pull request #1558 from antmicro/msieron/sdram-spd 
liblitedram: SPD read improvements
 2023-01-10 09:40:44 +01:00
enjoy-digital
222356d68e
Merge pull request #1559 from enjoy-digital/wishbone_dma_reader 
cores/dma/WishboneDMAReader: Add FIFO to pipeline reads and allow bust on Wishbone.
 2023-01-10 09:36:47 +01:00
Florent Kermarrec
25ea4a07ae cores/dma/WishboneDMAReader: Add FIFO to pipeline reads and allow burst on Wishbone. 2023-01-10 09:35:57 +01:00
Michal Sieron
7fbf66b1a4 bios/main: pretty print memory sizes 
Always print MAIN-RAM and optionally print SDRAM.
This is caused by the fact, that SDRAM size can be bigger than
RAM declared in the memory map.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:29:01 +01:00
Michal Sieron
bc592c0f71 liblitedram/utils: add get_supported_memory 
Add `get_supported_memory` function that reads SPD to calculate
supported memory from the SDRAM.
When it's not possible to read from the SPD (no I2C) or there are errors
with the readout, it defaults to `SDRAM_PHY_SUPPORTED_MEMORY` defined in
`generated/sdram_phy.h` by `litedram/init.py`.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:26:07 +01:00
Michal Sieron
08d439f021 soc/integration/builder: pass geom_settings when generating sdram_phy.h 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:26:07 +01:00
Michal Sieron
fb068f6e4e liblitedram: create utils.c 
Right now there are only `print_size` and `print_progress` functions
from memtest.c, but changed to use uint64_t.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:24:06 +01:00
Michal Sieron
2bdf04c19e cmds/cmd_litedram: read entire SPD 
Make use of added function `sdram_read_spd` to read entire SPD.
Also a typo fix.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:22:09 +01:00
Michal Sieron
39a8ca6fb6 liblitedram: add sdram_spd.c 
Add generic `sdram_read_spd` function which allows to read SPD data
with no need to think about paging.

Just provide SPD address, address from which you want to read the data,
buffer and length of the data.

Paging is taken care of inside the function.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:19:15 +01:00
enjoy-digital
0440733fc0
Merge pull request #1553 from stone3311/master 
clock/intel: Add Stratix V PLL parameters
 2023-01-05 22:08:06 +01:00
stone3311
9443bfcd8f clock/intel: Edit copyright 2023-01-05 19:10:18 +01:00
enjoy-digital
c5c332fa56
Merge pull request #1551 from eli-schwartz/versioncheck 
replace Meson version check with a specification-compliant version comparator
 2023-01-04 10:36:37 +01:00
Eli Schwartz
c4ec49e125
replace Meson version check with a specification-compliant version comparator 
The current check compares the integers split out from `meson --version`
one by one. This is an ad-hoc version comparison algorithm with a few
flaws, notably that it doesn't truly understand how version components
fit together, and that broke once Meson bumped the major version. There
are other potential issues that could show up but haven't yet, such as
versions with words in them (release candidates).

The packaging module is a high-quality library that provides a standard
version parsing algorithm, with which you can simply say "is this
version object greater than that one". Use it instead.

Fixes #1545
 2023-01-03 19:07:50 -05:00
stone3311
94ec68dd3c clock/intel: Add Stratix V PLL parameters 2023-01-03 14:07:03 +01:00
enjoy-digital
19e0e2fe8d
Merge pull request #1549 from antmicro/msieron/vivado-verilog-include-paths-fix 
build/xilinx/vivado: fix verilog include paths
 2023-01-02 18:22:27 +01:00
Michal Sieron
bd82a7b888 build/xilinx/vivado: fix verilog include paths 
a286d77e introduced a bug, where `-include_dirs` parameter is
incorrectly defined.

Following TCL code is being generated:
```tcl
synth_design -directive default -top digilent_arty -part xc7a35ticsg324-1L -include_dirs \{.join(self.platform.verilog_include_paths)}\}
```

Below is an explanation why it didn't work:
Python's f-strings escape curly braces using double curly braces like so
`{{` instead of using backslash `\{`.
What's more, you need to alternate single and double quotations marks
when using strings in curly braces expression otherwise two string
objects are being generated and errors like this one can happen.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-02 14:19:42 +01:00
Florent Kermarrec
3dee741bac litex_setup.py: Add --release argument to create a LiteX release with a specific tag. 2023-01-02 09:21:49 +01:00
Florent Kermarrec
c307bf28eb CHANGES.md: Prepare 2022.12 release. 2023-01-02 08:53:19 +01:00
enjoy-digital
3bf2473c7d
Merge pull request #1548 from stone3311/master 
cores/jtag: Add more Altera part numbers
 2023-01-01 14:34:40 +01:00
stone3311
f8d2f1adde cores/jtag: Add more Altera part numbers 2022-12-31 14:21:13 +01:00
enjoy-digital
99d67f9e5e
Merge pull request #1547 from navan93/patch-1 
Fix WID in axi versions
 2022-12-30 21:28:26 +01:00
enjoy-digital
01a4ea169c
Merge pull request #1546 from antmicro/fix_meson_version_check 
builder: Fix logic for determining meson version compatibility
 2022-12-30 21:27:48 +01:00
Navaneeth Bhardwaj
c1c9dc456c
Fix WID in axi versions 
There is no WID in AXI4
 2022-12-29 12:34:49 +05:30
Tomasz Michalak
9e2a00d71f builder: Fix logic for determining meson version compatibility 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2022-12-27 11:37:14 +01:00
enjoy-digital
e8322587a0
Merge pull request #1543 from stone3311/master 
build/altera: Fix IP integration
 2022-12-23 19:50:19 +01:00