Sebastien Bourdeauducq
|
80970b203c
|
bus/asmibus: use implicit finalization
|
2013-03-11 17:11:59 +01:00 |
|
Sebastien Bourdeauducq
|
b042757187
|
Fix Register name conflict between Pytholite and Bank
|
2013-03-10 19:47:21 +01:00 |
|
Sebastien Bourdeauducq
|
f93695f60e
|
bank/eventmanager: use module and autoreg
|
2013-03-10 19:29:05 +01:00 |
|
Sebastien Bourdeauducq
|
174e8cb8d6
|
bus/asmibus: use fhdl.module API
|
2013-03-10 19:28:22 +01:00 |
|
Sebastien Bourdeauducq
|
17e0dfe120
|
fhdl/module: replace autofragment
|
2013-03-10 19:27:55 +01:00 |
|
Sebastien Bourdeauducq
|
cddbc1157d
|
bank/description/AutoReg: check that get_memories and get_registers are callable
|
2013-03-10 18:11:29 +01:00 |
|
Sebastien Bourdeauducq
|
68fe4c269c
|
bank/csrgen: BankArray
|
2013-03-10 00:45:16 +01:00 |
|
Sebastien Bourdeauducq
|
f1474420df
|
bank/description: AutoReg
|
2013-03-10 00:43:16 +01:00 |
|
Sebastien Bourdeauducq
|
d0676e2dd1
|
migen/fhdl/autofragment: factorize
|
2013-03-09 23:23:24 +01:00 |
|
Sebastien Bourdeauducq
|
d0d2df3c4b
|
fhdl/autofragment: remove legacy functions
|
2013-03-09 23:05:45 +01:00 |
|
Sebastien Bourdeauducq
|
72fb6fd6bd
|
fhdl/tools/flat_iteration: generalize
|
2013-03-09 23:03:15 +01:00 |
|
Sebastien Bourdeauducq
|
f53acb92e7
|
fhdl/autofragment: fix submodules
|
2013-03-09 21:15:38 +01:00 |
|
Sebastien Bourdeauducq
|
6da8eb906f
|
fhdl/autofragment: empty build_fragment by default
|
2013-03-09 19:10:47 +01:00 |
|
Sebastien Bourdeauducq
|
2b8dc52c13
|
Use common definition for FinalizeError
|
2013-03-09 19:03:13 +01:00 |
|
Sebastien Bourdeauducq
|
b75fb7f97c
|
csr/SRAM: support for writes with memory widths larger than bus words
|
2013-03-09 00:50:57 +01:00 |
|
Sebastien Bourdeauducq
|
6fa30053bf
|
fhdl/verilog: tristate outputs are always wire
|
2013-03-06 11:30:52 +01:00 |
|
Sebastien Bourdeauducq
|
9b4ca987e0
|
bus/csr: support memories with larger word width than the bus (read only)
|
2013-03-03 19:27:13 +01:00 |
|
Sebastien Bourdeauducq
|
bb5ee8d3bd
|
fhdl/autofragment: bugfixes + add auto_attr
|
2013-03-03 17:53:06 +01:00 |
|
Sebastien Bourdeauducq
|
cc8118d35c
|
fhdl/autofragment: FModule
|
2013-03-02 23:30:54 +01:00 |
|
Sebastien Bourdeauducq
|
d2491828a4
|
csr/SRAM: prefix page register with memory name
|
2013-03-01 12:06:12 +01:00 |
|
Sebastien Bourdeauducq
|
c10622f5e2
|
fhdl/verilog: insert reset before listing signals
|
2013-02-27 18:10:04 +01:00 |
|
Sebastien Bourdeauducq
|
d2cbc70190
|
bank/description: memprefix
|
2013-02-25 23:14:15 +01:00 |
|
Sebastien Bourdeauducq
|
a81781f589
|
fhdl/specials: allow setting memory name
|
2013-02-25 23:14:03 +01:00 |
|
Sebastien Bourdeauducq
|
425de02f42
|
uio/ioo: fix specials
|
2013-02-25 23:13:38 +01:00 |
|
Sebastien Bourdeauducq
|
55ab01f928
|
fhdl/specials/Instance: _printintbool -> verilog_printexpr
|
2013-02-24 13:08:01 +01:00 |
|
Sebastien Bourdeauducq
|
c2d54f481f
|
examples/psync: cleanup
|
2013-02-23 19:14:31 +01:00 |
|
Sebastien Bourdeauducq
|
6abac5907b
|
examples/basic/psync: demonstrate the new features
|
2013-02-23 19:04:11 +01:00 |
|
Sebastien Bourdeauducq
|
a878db1e3c
|
genlib: clock domain crossing elements
|
2013-02-23 19:03:35 +01:00 |
|
Sebastien Bourdeauducq
|
7c4e6c35e5
|
fhdl/verilog: support special lowering and overrides
|
2013-02-23 19:03:16 +01:00 |
|
Sebastien Bourdeauducq
|
3a591c358c
|
examples/fir: better filter
|
2013-02-22 23:19:56 +01:00 |
|
Sebastien Bourdeauducq
|
f9acee4e68
|
corelogic -> genlib
|
2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
|
38664d6e16
|
fhdl: inline synthesis directive support
|
2013-02-22 19:10:02 +01:00 |
|
Sebastien Bourdeauducq
|
587f50cf90
|
doc: new 'specials' API
|
2013-02-22 18:12:42 +01:00 |
|
Sebastien Bourdeauducq
|
49cfba50fa
|
New 'specials' API
|
2013-02-22 17:56:35 +01:00 |
|
Sebastien Bourdeauducq
|
e82ea19cdc
|
doc: tristates
|
2013-02-19 17:52:57 +01:00 |
|
Sebastien Bourdeauducq
|
1b18194b1d
|
fhdl: TSTriple
|
2013-02-19 17:26:02 +01:00 |
|
Sebastien Bourdeauducq
|
dc93a231c6
|
fhdl: tristate support
|
2013-02-15 00:17:24 +01:00 |
|
Sebastien Bourdeauducq
|
63d399b6ad
|
fhdl/autofragment: from_attributes
|
2013-02-11 18:34:01 +01:00 |
|
Sebastien Bourdeauducq
|
7ff61d8930
|
doc: fix signal desc layout
|
2013-02-10 19:39:18 +01:00 |
|
Sebastien Bourdeauducq
|
d78fc48805
|
Merge branch 'master' of github.com:milkymist/migen
|
2013-02-10 19:03:32 +01:00 |
|
Sebastien Bourdeauducq
|
1794b45ed3
|
doc/dataflow: remove ActorNode
|
2013-02-10 19:03:18 +01:00 |
|
Sebastien Bourdeauducq
|
f2665efbfe
|
doc/dataflow: remove ALA
|
2013-02-10 18:57:03 +01:00 |
|
Sebastien Bourdeauducq
|
b988003878
|
doc: multiple clock domains
|
2013-02-10 18:56:45 +01:00 |
|
Sebastien Bourdeauducq
|
6bca9c8b98
|
doc: do not inline examples as this never works with most Sphinx setups ...
|
2013-02-10 18:45:06 +01:00 |
|
Sebastien Bourdeauducq
|
3f063db281
|
doc: update to new Migen APIs
|
2013-02-10 18:42:47 +01:00 |
|
Sebastien Bourdeauducq
|
92b67df41c
|
sim: default runner to Icarus Verilog
|
2013-02-09 17:04:53 +01:00 |
|
Sebastien Bourdeauducq
|
bd6856ba7a
|
flow/perftools: finish removing ActorNode
|
2013-02-09 17:03:48 +01:00 |
|
Sebastien Bourdeauducq
|
473fd20f8c
|
fhdl/structure: store clock domain name
|
2013-01-24 13:49:49 +01:00 |
|
Sebastien Bourdeauducq
|
3201554f76
|
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
|
2013-01-23 15:13:06 +01:00 |
|
Sebastien Bourdeauducq
|
314a6c7743
|
corelogic: complex arithmetic support
|
2013-01-05 14:18:36 +01:00 |