Adds a switch `--with-gpio`, which will add a 32 pin GPIOTristate
core, with the GPIOTristate signals exposed on the top-level
module. This can be used to add a custom GPIO module in the Verilated
simulation.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
Support exposing tristate GPIOs with tristate pads, by avoiding
instantiation of tristate buffers directly in the module. This gives
the developers more flexibility in how they want to implement their
tristate IOs (for example with level shifters behind the IOs), and
allows to use the GPIOTristate core in the Verilated simulation as
Verilator does not support top-level inout signals.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
On slow configurations (ex iCEBreaker / SERV CPU / 12MHz SPI Flash freq) memspeed test was
too slow (>200s to do the random test for 1MB), so reduce test size to 4KB.
This will be less accurate but will still provide representative results which
is the aim of this test.
Integration from #1024 was working on some boards (ex Arty) but breaking others (ex iCEBreaker);
simplify things for now:
- Avoid duplication in spiflash_freq_init.
- Avoid passing useless SPIFLASH_LEGACY flag to software (software can detect it from csr.h).
- Only keep integration support for "legacy" PHY, others are not generic enough and can be passed with phy parameter.
litex_sim: SoC without RAM/SDRAM.
litex_sim --integrated-main-ram-size=0x1000: SoC with RAM of size 0x1000.
litex_sim --with-sdram: SoC with SDRAM.
litex_sim --integrated-main-ram-size=0x1000 --with-sdram: SoC with RAM (priority to RAM over SDRAM).
Inside the litex add_spi_flash function
we are detecting the devices that can't be used with
more efficient DDR version of litespi phy core
and we are choosing whether to instantiate the legacy or DDR core
When building with GCC 11:
../libbase/crt0.o: in function `_start':
litex/soc/cores/cpu/microwatt/crt0.S:54:(.text+0x38): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fdata' defined in .data section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:55:(.text+0x3c): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_edata' defined in .data section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:56:(.text+0x40): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fdata_rom' defined in *ABS* section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:68:(.text+0x68): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fbss' defined in .bss section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:69:(.text+0x6c): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_ebss' defined in .bss section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:80:(.text+0x90): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fstack' defined in .bss section in bios.elf
boot.o: in function `copy_file_from_sdcard_to_ram':
litex/soc/software/bios/boot.c:622:(.text+0x18): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'
litex/soc/software/bios/boot.c:627:(.text+0x5c): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'+8
litex/soc/software/bios/boot.c:633:(.text+0x8c): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'+10
litex/soc/software/bios/boot.c:639:(.text+0xdc): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'+18
litex/soc/software/bios/boot.c:650:(.text+0x128): additional relocation overflows omitted from the output
This is because we pass -mcmodel=small. As the PowerPC ELF ABI
describes, the small code model restricts the relocations to 16-bit
offsets[1]. If we omit the option we get the default, which is the
medium model allowing 32-bit offsets.
http://openpowerfoundation.org/wp-content/uploads/resources/leabi/content/dbdoclet.50655240_19143.html
Signed-off-by: Joel Stanley <joel@jms.id.au>
New version of binutils contain stricter checks for sections that are
not included in the linker script, resulting in this error:
ld: error: no memory region specified for loadable section `.note.gnu.build-id'
Disable this feature as there is no use for it on bare metal systems.
Signed-off-by: Joel Stanley <joel@jms.id.au>
binutils 2.34 contains stricter checks for sections that are not
included in the linker script, resulting in this error:
ld: bios.elf: error: PHDR segment not covered by LOAD segment
From the 2.34 NEWS:
The ld check for "PHDR segment not covered by LOAD segment" is more
effective, catching cases that were wrongly allowed by previous versions of
ld. If you see this error it is likely you are linking with a bad linker
script or the binary you are building is not intended to be loaded by a
dynamic loader. In the latter case --no-dynamic-linker is appropriate.
As the BIOS runs bare metal, we do not need to emit a PHDR segment.
Signed-off-by: Joel Stanley <joel@jms.id.au>
This patch adds the static files needed for the documentation to the
`package_data` field in `setup.py`.
I ran into failures when generating documentation after installing litex
using pipenv which didn't copy these files which in turn caused the
documentation generation to fail.
This change causes all files in the `static` subfolder of the
litex.soc.doc module to be installed as well.
READ_CHECK_TEST_PATTERN_MAX_ERRORS was being computed incorrectly
which could result in integer underflows when computing core via
(max_errors - errors). This could happen e.g. when using
DFIRateConverter, which modifies DFII_PIX_DATA_BYTES. Now we use
DFII_PIX_DATA_BYTES in the equation so this should not happen.
The Linux LiteETH driver parses registers by name. Provide the expected
names for each register: "mac", "mdio", and "buffer", respectively.
For setting up tx and rx slots, the Linux driver expects three pieces
of information: number of tx and rx slots, and slot size. Update
json2dts_linux to provide the appropriate names and values.
When playing with CPUs and variants, users previously had to do a rm -rf build to ensure
a proper software build. Various developers already lost time on it so it's important
to handle it directly in the Builder which is now the case.
-litex_json2dts_linux (previously litex_json2dts).
-litex_json2dts_zephyr (previously litex_zephyr_dts_generator).
-litex_json2renode (previously litex_renode_generator).
litex_json2dts_zephyr and litex_json2renode are now also directly exposed.
- Fix compilation in sdram.c.
- Fix warnings.
- Move Sequential/Random mode printf to memtest.
- Reduce SPI Flash test size (Testing full SPI Flash makes the boot too long, especially in random mode).
Leon Schuermann
Florent Kermarrec
wuhanstudio
Tim Ansell
Pawel Sagan
Piotr Binkowski
Tim Callahan
Joel Stanley
Andreas Galauner
asadaleem-rs
Jędrzej Boczar
Michal Sieron
Gabriel Somlo