Florent Kermarrec
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718c26d8fc
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cpu/gowin_emcu: Add interfaces directly to instances and simplify/cleanup to remove some warnings.
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2024-01-04 19:33:43 +01:00 |
|
Florent Kermarrec
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c61d2de13b
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CHANGES.md: Update.
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2024-01-04 15:37:58 +01:00 |
|
Florent Kermarrec
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cf165d3c2c
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README/Bios: Bump year.
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2024-01-04 15:33:01 +01:00 |
|
Florent Kermarrec
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739a8db8c3
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cpu/gowin_emcu: Specify AHB data_width/address_width.
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2024-01-04 15:30:47 +01:00 |
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Florent Kermarrec
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7009299132
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interconnect/ahb: Simplify AHBInterface and add data_width/address_width parameters.
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2024-01-04 15:30:26 +01:00 |
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Florent Kermarrec
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02f0a96c84
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interconnect/ahb: Add AHB prefix to TransferType/Interface (similar to AXI).
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2024-01-04 15:21:32 +01:00 |
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Florent Kermarrec
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55e2a1cec6
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cpu/gowin_emcu: Switch pbus to byte addresssing.
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2024-01-04 13:13:21 +01:00 |
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Florent Kermarrec
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5bbcda4d5c
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interconnect/ahb/AHB2Wishbone: Fix size check that is too restrictive, can be <= log2_int(ahb.data_width//8).
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2024-01-04 13:12:29 +01:00 |
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Florent Kermarrec
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6a6837062a
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cpu/gowin_emcu: Remove interrupt signal since not yet functional/used.
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2024-01-04 10:40:47 +01:00 |
|
Florent Kermarrec
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386854cbd3
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cpu/gowin_emcu: Use crt0.c from cortex_m3.
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2024-01-04 10:38:45 +01:00 |
|
Florent Kermarrec
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de6fbf1271
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cpu/gowin_emcu: Directly connect AHB interfaces, using for loops make things unclear/difficult to follow.
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2024-01-04 10:33:50 +01:00 |
|
Florent Kermarrec
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b0cde1acdd
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cpu/gowin_emcu: Switch SRAM to 4 SRAMS of 8-bit each.
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2024-01-04 10:12:36 +01:00 |
|
Florent Kermarrec
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01520cd638
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cpu/gowin_emcu: Simplify SRAM.
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2024-01-04 09:59:17 +01:00 |
|
Florent Kermarrec
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6d3c955d59
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cpu/gowin_emcu: Increase similarities with cortex_m3 (since gowin_emcu is a Cortex M3).
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2024-01-04 09:09:18 +01:00 |
|
Florent Kermarrec
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85ef3bd8a7
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cpu/gowin_emcu: Add missing reset signals.
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2024-01-03 19:41:03 +01:00 |
|
Florent Kermarrec
|
3f9de470f6
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cpu/gowin_emcu: Add gcc_flags method and set UART_POLLING in it.
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2024-01-03 19:15:46 +01:00 |
|
Florent Kermarrec
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456dda050c
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cpu/gowin_emcu: Cleanup/Simplify.
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2024-01-03 19:11:05 +01:00 |
|
Florent Kermarrec
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3909b1d611
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build/openfpgaloader: Add kwargs support to flash method and some comments.
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2024-01-02 13:50:02 +01:00 |
gsomlo
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acf07a21c9
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soc: fix typo in cpu mem_bus axi-via-wb downconvert (#1865)
Fixes: 002aad7a4
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2024-01-01 13:32:40 -05:00 |
|
enjoy-digital
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56f61986f0
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Merge pull request #1862 from dau-dev/tkp/classifiers
Fix classifiers to satisfy format checks
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2023-12-31 19:17:43 +01:00 |
Tim Paine
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68cfb6eea0
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Fix classifiers to satisfy format checks
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2023-12-28 15:49:31 -05:00 |
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Florent Kermarrec
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67cfcadf79
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setup.py/CHANGES.md: Prepare 2023.12 release.
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2023-12-25 15:36:10 +01:00 |
Gwenhael Goavec-Merou
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7062e3379f
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build/efinix/ifacewriter: bypass clks out frequency check for Trion when a feedback clock is used
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2023-12-20 20:33:15 +01:00 |
|
Gwenhael Goavec-Merou
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54c58ef8b9
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build/efinix/ifacewriter: reorder FEEDBACK for Trion devices.
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2023-12-20 20:29:23 +01:00 |
|
Gwenhael Goavec-Merou
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7d5de90a24
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soc/cores/clock/efinix: remove 2 output clocks limit, reset o_div_max when a nex vco_max_freq is found
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2023-12-20 20:28:51 +01:00 |
|
Florent Kermarrec
|
040b554022
|
CHANGES.md: Update.
|
2023-12-20 16:11:12 +01:00 |
|
Florent Kermarrec
|
23fbd1b334
|
CHANGES.md: Update.
|
2023-12-20 16:10:03 +01:00 |
|
Florent Kermarrec
|
4721029e58
|
CHANGES.md: Update.
|
2023-12-20 15:25:14 +01:00 |
|
Florent Kermarrec
|
fadea1d31b
|
CHANGES.md: Update.
|
2023-12-20 08:08:42 +01:00 |
|
Gwenhael Goavec-Merou
|
cd503bc9af
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build/efinix/ifacewriter: Titanium PLL's feedback clock
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2023-12-19 21:25:59 +01:00 |
|
Florent Kermarrec
|
048c42820c
|
setup.py: Switch minimum Python version to 3.7 (To allow more than 255 arguments in functions).
|
2023-12-19 10:32:12 +01:00 |
|
Florent Kermarrec
|
33c07a094e
|
setup.py: Specify UTF-8 encoding for long_description/README.md.
|
2023-12-19 10:16:15 +01:00 |
|
Florent Kermarrec
|
0c3cda3ee8
|
CHANGES.md: Update.
|
2023-12-19 10:09:44 +01:00 |
|
Florent Kermarrec
|
2318ff37d2
|
setup.py: Improve indentation.
|
2023-12-19 10:08:40 +01:00 |
|
Florent Kermarrec
|
b6e89c646e
|
CHANGES: Update.
|
2023-12-14 11:08:55 +01:00 |
|
Gwenhael Goavec-Merou
|
84e376efcb
|
build/openocd: jtagstream_rxtx reduce tx to 16 and rx to 128
|
2023-12-13 15:08:18 +01:00 |
|
enjoy-digital
|
cdd80a5f4f
|
Merge pull request #1433 from tpwrules/faster-jtaguart
Increase JTAG UART upload speed
|
2023-12-13 15:05:37 +01:00 |
|
enjoy-digital
|
5dac2fc16f
|
Merge pull request #1852 from trabucayre/increase_cmd_timeout_delay
soc/software/bios/boot: serialboot: increase CMD_TIMEOUT_DELAY
|
2023-12-13 14:39:17 +01:00 |
|
Gwenhael Goavec-Merou
|
00b94a5512
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soc/software/bios/boot: serialboot: increase CMD_TIMEOUT_DELAY
|
2023-12-13 14:29:54 +01:00 |
|
Florent Kermarrec
|
faae1ea95a
|
integration/soc/jtag: Switch JTAGPHY to sys_clk/simplify.
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2023-12-13 09:24:23 +01:00 |
|
Florent Kermarrec
|
4e57cca85f
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cpu/vexriscv: Cleanup reset.
|
2023-12-13 09:17:15 +01:00 |
|
Florent Kermarrec
|
f2c5ff376c
|
soc/cores/jtag: Switch to stream.ClockDomainCrossing and use common_rst.
|
2023-12-13 09:16:55 +01:00 |
|
Gwenhael Goavec-Merou
|
94eca8628c
|
Revert "soc/integration/soc: add_sdram, remove litedram_wb and converter: let LiteDRAMWishbone2Native dealing with addr/data width"
This reverts commit 6d34b8ed87.
|
2023-12-12 15:19:16 +01:00 |
|
Gwenhael Goavec-Merou
|
6d34b8ed87
|
soc/integration/soc: add_sdram, remove litedram_wb and converter: let LiteDRAMWishbone2Native dealing with addr/data width
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2023-12-12 12:05:47 +01:00 |
|
Gwenhael Goavec-Merou
|
08ff003178
|
tools/litex_server.py: jtag/udp mode: add missing addr_width parameter
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2023-12-09 06:08:53 +01:00 |
|
Gwenhael Goavec-Merou
|
c1871eaf42
|
soc/integration/soc: add_jtagbone: pass address_width to UARTBone constructor
|
2023-12-09 06:07:58 +01:00 |
|
Florent Kermarrec
|
acd66f1346
|
soc/bus_addressing_convert: Fix s2m adaptation case, the 2 adaptation cases were swapped.
|
2023-12-08 15:25:30 +01:00 |
|
Florent Kermarrec
|
8d6120c476
|
CHANGES: Update.
|
2023-12-08 12:11:37 +01:00 |
|
enjoy-digital
|
1e5df2dedf
|
Merge pull request #1851 from trabucayre/add_64_bus_support_v2
Add AXI/AXILite 64 bus support
|
2023-12-08 12:08:09 +01:00 |
|
Gwenhael Goavec-Merou
|
2134c0d0b0
|
soc/integration/soc: when adding a CSR Bridge bus_bridge must keep bus.address_width instead of the default value
|
2023-12-08 12:02:45 +01:00 |