Commit Graph

7869 Commits

Author SHA1 Message Date
Michal Sieron 6bff5f1734 Replace inet.h with arpa/inet.h 2021-09-16 10:42:54 +02:00
Michal Sieron 082d1231f6 Remove obsolete time.c 2021-09-16 10:42:54 +02:00
Michal Sieron 823edfad22 Remove obsolete div64.c 2021-09-16 10:42:54 +02:00
Michal Sieron 8e4e3b5438 Enable LTO
Use gcc-ar and gcc-nm, because they have LTO plugins

Turn off LTO for libcompiler_rt, exchange.c and arc4random.c
from newlib.

Also add getentropy, dummy function, because for some reason
libbase/console.c wants it.
2021-09-16 10:42:29 +02:00
Michal Sieron 53135eb7bc Add missing definitions if target is microwatt
Picolibc compilation for powerpc was missing some defines.
This adds them to gcc parameters
2021-09-16 10:41:05 +02:00
Michal Sieron ba1d20f2ad Add missing functions to make lm32 and or1k link
I added missing.c with functions that were preventing
LiteX from successfull linking on lm32 and or1k.
2021-09-16 10:41:05 +02:00
Michal Sieron 4e50c0ba00 Enable global errno
Brings mor1kx compilation to the same error as lm32
2021-09-16 10:41:05 +02:00
Michal Sieron ab881c561f Implement initial support for lm32 and or1k
Picolibc doesn't maintain meson.build or cross*.txt files
for lm32 and or1k CPUs.

This commit adds meson.build files for both of them.
Also libc/Makefile got modifed to determine CPU family
from $(CPU) value and generate cross.txt file.
Now picolibc gets compiled with LiteX flags too.

It doesn't compile on neither of them yet,
but at least riscv still works.
2021-09-16 10:41:05 +02:00
Michal Sieron ca4e17d886 Disable float support in tinystdio
Float support was originally disabled in libbase
2021-09-16 10:41:05 +02:00
Michal Sieron b34adcf929 Remove libbase-nofloat.a variant
As vsnprintf is no longer compiled it was
identical to libbase.a.

Picolibc defines levels of printf and scanf
https://github.com/picolibc/picolibc/blob/main/doc/printf.md#printf-and-scanf-levels-in-picolibc
so those should probably be used.
2021-09-16 10:41:05 +02:00
Michal Sieron c4ba313b86 Remove unnecessary header and source files 2021-09-16 10:41:05 +02:00
Michal Sieron a6094fd418 Move libbase/console.c logic to libc/iob.c 2021-09-16 10:41:05 +02:00
Michal Sieron 768961ec59 Use getchar/putchar instead of readchar/base_putchar 2021-09-16 10:41:05 +02:00
Michal Sieron ead3f8b2e0 Compile iob.c with $(compile) 2021-09-16 10:41:05 +02:00
Michal Sieron 8a38a79967 Remove unnecessary headers 2021-09-16 10:41:05 +02:00
Michal Sieron 10927691c5 Remove base and add picolibc to include search paths 2021-09-16 10:41:05 +02:00
Michal Sieron 19966edb61 Replace putsnonl(s) with fputs(s, stdout)
It won't compile, because stdout is undefined, but
including headers from picolibc should fix that
2021-09-16 10:41:05 +02:00
Michal Sieron acf3a4570b Create __iob for picolibc
Picolibc requires __iob array for its IO functions

This commit creates such array with dummy functions
using putchar/readchar from console.c

To prevent name conflicts printf and others were
removed from console.c

Also putchar had to be renamed to base_putchar
2021-09-16 10:41:05 +02:00
Michal Sieron db390537a9 Compile entire picolibc
It does not compile yet, will need __iob array to be defined
Also there are multiple definitions of some functions
2021-09-16 10:41:05 +02:00
Michal Sieron 514754bedf Get pythondata-software-picolibc from antmicro 2021-09-16 10:41:05 +02:00
Michal Sieron fc0fa88e33 Update litex_setup.py to use forked codebase 2021-09-16 10:41:05 +02:00
Michal Sieron 6de59bdbc0 Incorporate picolibc into the build process
Right now it is still limited as it compiles only for one target,
but it should be possible to build BIOS with one command

Tested with digilent_arty.py
2021-09-16 10:41:05 +02:00
Michał Sieroń e25ca4082b Apply patch removing need for most of libbase 2021-09-16 10:41:05 +02:00
Florent Kermarrec beb7cc691d CHANGES: Do 2021.08 release. 2021-09-15 15:05:47 +02:00
Florent Kermarrec 343d88e837 setup.py: Expose litex_contributors tool. 2021-09-15 14:38:45 +02:00
Florent Kermarrec 05b960d09b CHANGES: Update. 2021-09-15 12:08:30 +02:00
enjoy-digital 02896a4a30
Merge pull request #1037 from thirtythreeforty/ecp5-pll
Fix premature selection of full PLL config with no feedback
2021-09-15 08:52:59 +02:00
George Hilliard 91ec6e0da8 clock/lattice_ecp5/ECP5PLL: emit frequency annotations to help Diamond
Unlike nextpnr, Diamond appears not to infer the frequency of the
outputs.  Emit the same attributes that Diamond's PLL tool does.
2021-09-15 00:07:43 -05:00
George Hilliard 6733a3e3e6 clock/lattice_ecp5/ECP5PLL: ensure feedback path selected before exiting search 2021-09-15 00:07:43 -05:00
Florent Kermarrec 88d302d4db soc/alloc_region: Ensure allocated Region is aligned on size. 2021-09-14 18:08:07 +02:00
Florent Kermarrec 694878a35a integration/soc/add_ethernet/etherbone: Add with_timing_constraints parameter to allow disabling constraints.
Some boards require specific constraints, so disable them in this case and put constraints in the target file.
2021-09-13 19:32:50 +02:00
Leon Schuermann 8670ac4902 litex_sim: add optional GPIOTristate core
Adds a switch `--with-gpio`, which will add a 32 pin GPIOTristate
core, with the GPIOTristate signals exposed on the top-level
module. This can be used to add a custom GPIO module in the Verilated
simulation.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-13 12:33:41 +02:00
Florent Kermarrec cb7b0f44cf tools/litex_sim: Fix mem_map. 2021-09-13 11:33:16 +02:00
Leon Schuermann af8459301c litex/soc/cores/gpio: support external tristate buffer
Support exposing tristate GPIOs with tristate pads, by avoiding
instantiation of tristate buffers directly in the module. This gives
the developers more flexibility in how they want to implement their
tristate IOs (for example with level shifters behind the IOs), and
allows to use the GPIOTristate core in the Verilated simulation as
Verilator does not support top-level inout signals.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-13 11:17:54 +02:00
Camilo Andres Vera Ruiz a235eaf0cd
Linker fix for initialized global variables
I found that in some cases, initialized global variables don't work with user libraries, so a little change to the linker that I use, taken from the demo file, seems to solve the problem . I think that make more sense to put the global variables in sram and initial values in the main_ram, similar to the bios linker.
2021-09-13 00:44:30 -05:00
Stafford Horne ea06948c62 json2dts_linux: Add configuration for root device
This allows setting a root device other than ram0, this is useful
when using a rootfs from the SD card.  Doing this makes boot time
faster and saves on memory footprint used by an in ram initrd.
2021-09-12 14:44:22 +09:00
Stafford Horne ec2f2a6af5 json2dts_linux: Use liteuart earlycon
Now that liteuart earlycon is upstream we can use it.  This means
all litex soc's should be able to get an earlycon now.  Tested on
mor1kx.
2021-09-12 14:42:52 +09:00
Stafford Horne 378d129c5f json2dts_linux: Allow disabling of initrd 2021-09-12 14:42:46 +09:00
Leon Schuermann a568b7e26a test_packet.py: test randomly generated headers
Also includes some fixes for the non-last_be test path such that the
expected behavior is the one currently oberserved with the Packetizer
and Depacketizer.
2021-09-10 15:30:05 +02:00
Leon Schuermann 958bcaad2e test_packet.py: add last_be tests 2021-09-10 12:30:04 +02:00
Leon Schuermann 037294dc3b test_packet.py: support passing debug_print parameter 2021-09-09 16:37:26 +02:00
Leon Schuermann 6bda383178 test_packet.py: support {Dep,P}acketizer behavior without last_be 2021-09-09 16:37:26 +02:00
Leon Schuermann 6cacdcd926 {Dep,p}acketizer: handle transactions of a single bus word 2021-09-09 16:36:21 +02:00
Leon Schuermann a08271b83a test_packet.py: utilize generic stream_inserter/colletor interface 2021-09-09 16:08:12 +02:00
Leon Schuermann ca50cba986 Rewrite test_stream.py with reusable stream_inserter/collector 2021-09-09 16:08:12 +02:00
Leon Schuermann 2e8586a090 {Dep,P}acketizer: properly handle last_be wraparound
While the Depacketizer did correctly calculate a new last_be value for
the data with the header removed, it may happen that the last_be
overflows and thus relates to the current, non-delayed sink value. The
same goes for the Packetizer, just inversed. This introduces logic in
form of a simple FSM to handle these cases and properly output last_be
on the last valid bus word.

Co-authored-by: David Sawatzke <d-git@sawatzke.dev>
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-09 16:08:12 +02:00
Nathaniel R. Lewis 9ec45181dd .gitignore: ignore visual studio code settings 2021-09-08 18:06:45 -07:00
Nathaniel R. Lewis ab3d7e86f2 litex/tools: add command line options and fixes for lxterm to allow crossover uart over PCIe 2021-09-08 18:06:12 -07:00
Florent Kermarrec e0e9311ceb interconnect/wishbone: Specify Wishbone version (#999). 2021-09-08 17:33:01 +02:00
Florent Kermarrec 6c2bc02323 build/xilinx/vivado: Add XilinxVivadoCommands for pre_synthesis/placement/routing_commands with add method to automatically resolve LiteX signals'names.
This makes it similar to add_platform_command and add more flexibility to constraint the design.
2021-09-08 16:14:58 +02:00