4014fbffe1
soc_core/add_memory_region: fix memory overlap detection
2019-10-28 17:07:37 +01:00
650df0ebc2
test/test_targets: skip Minerva test on Travis-CI, remove commented tests
2019-10-28 11:00:08 +01:00
ab8af28213
cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier
2019-10-28 10:23:08 +01:00
4cc40aadaa
Merge pull request #286 from gsomlo/gls-timingstrict
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build/lattice/trellis: optionally allow failure if p&r timing not met
2019-10-25 12:28:29 +02:00
49372852da
build/lattice/trellis: optionally allow failure if p&r timing not met
...
When timing requirements are strict, allow the build process to fail upon
failure to meet timing. This facilitates running the build process from a
loop, repeatedly, until a "lucky" p&r solution is found, e.g.:
while true; do
litex/boards/targets/versa_ecp5.py --gateware-toolchain trellis \
--sys-clk-freq=60e06 --cpu-type rocket --cpu-variant linux \
--with-ethernet --yosys-nowidelut \
--nextpnr-timingstrict
if [ "$?" == "0" ]; then
echo "Success" | mail -s "Build Succeeded" your@email.here
break
fi
done
This augments commit #683e0668, which unconditionally forced p&r to
succeed, regardless of whether timing was met, via '--timing-allow-fail'.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-24 13:56:20 -04:00
b6d35c92ae
Merge pull request #283 from kbeckmann/kbeckmann/bios_increment_address
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bios: Increment address when writing to flash
2019-10-20 15:30:22 +02:00
ef78ae951f
bios: Increment address when writing to flash
2019-10-19 22:58:24 +02:00
683e066812
build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met
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This is the default behaviour of the others tools and allow testing designs on hardware with small violations.
2019-10-18 14:12:01 +02:00
4cf346a1d4
soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1
2019-10-18 10:27:37 +02:00
39862f068e
Merge pull request #282 from antmicro/icapbitstream_fixes
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Fix ICAPBitstream
2019-10-18 10:24:20 +02:00
8b5da9c623
cores/icap/ICAPBitstream: add source ready signal.
2019-10-18 09:33:31 +02:00
626533ce9d
soc/integration/__init__: remove imports (not used and causing issues
2019-10-17 12:44:37 +02:00
675b455259
build: always use platform.add_source and avoid manipulate platform.sources directly
2019-10-17 12:17:36 +02:00
43f5d1ef13
build/generic_platform: replace set with list for sources/verilog_include_paths
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Python does not have native OrderedSet and we need to be able to preserve the order of the sources
for some backends (Verilator for instance), so use list instead of set.
2019-10-17 09:52:49 +02:00
97a77b950c
cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it.
2019-10-16 15:00:58 +02:00
98c224be15
build/generic_platform: keep language to None if None after tools.language_by_filename
2019-10-15 12:14:37 +02:00
14dae8bd73
soc_core: fix default --uart_name
2019-10-14 22:15:02 +02:00
ba26441889
integration/soc_core: expose more SoC parameters
2019-10-14 09:12:25 +02:00
23d8396144
Merge pull request #280 from kbeckmann/picorv32_typo
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picorv32: Fix minimal variant params
2019-10-13 11:29:46 -07:00
0e467168fd
picorv32: Fix minimal variant params
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The param p_ENABLE_COUNTERS was misspelled.
2019-10-13 12:56:55 +02:00
ef504f62af
soc_core: fix soc_core_argdict
2019-10-12 23:05:53 +02:00
cd8213b988
cpu/lm32: add missing buses
2019-10-12 19:20:50 +02:00
5a0358754d
soc_core/soc_core_argdict: use inspect to get all parameters and simplify
2019-10-12 19:18:57 +02:00
96c369f3e4
integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo)
2019-10-11 21:55:26 +02:00
29e51f5e97
interconnect/wishbone: fix Converter case when buses are identical
2019-10-11 21:49:11 +02:00
ae9c25b74f
platforms/versa_ecp5: add serdes refclk/sma
2019-10-11 19:51:38 +02:00
9a82933858
cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore)
2019-10-11 09:01:50 +02:00
ca81cc209b
soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)
2019-10-11 09:01:08 +02:00
03faf06c82
soc/interconnect/axi: re-align to improve readability
2019-10-11 08:41:05 +02:00
7dea9afd7d
software/bios: simplify banners
2019-10-11 08:38:12 +02:00
6bd1889330
cpu/picorv32: remove obsolete comment
2019-10-10 22:29:54 +02:00
28517d20ca
cpu/picorv32: use a single idbus
2019-10-10 22:02:04 +02:00
5daf1a2296
cpu: cleanup/re-align
2019-10-10 21:52:09 +02:00
467d35edee
cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix
2019-10-10 21:40:29 +02:00
1045cda39e
cpu: add buses list and use it in soc_core to add bus masters
2019-10-10 21:35:06 +02:00
42ccc91f74
integration: move soc constants to soc.h of csr.h
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software retro-compat with soc.h included in csr.h
2019-10-10 21:15:49 +02:00
ed3c53d7cd
build/generic_platform: only add sources if language is not None
2019-10-10 19:39:33 +02:00
f3ba078882
xilinx/vivado: replace "xy" == language with language == "xy"
2019-10-10 19:36:17 +02:00
17756f631b
Merge pull request #277 from railnova/feature/vivado_sysverilog_support
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[feature] Add SystemVerilog support for the Vivado builder
2019-10-10 19:31:09 +02:00
b25194826e
integration/soc_zynq: shadow_base no longer recommended (replace with io_regions)
2019-10-10 19:23:01 +02:00
496ba7e594
bios/main: use same banner than README (MiSoC cited in README/LICENSE)
2019-10-10 19:21:32 +02:00
840f01b6d5
software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf
2019-10-10 19:18:28 +02:00
f2369a4c9e
Add system Verilog support for the Vivado builder
2019-10-10 14:10:28 +02:00
37531cec81
Merge pull request #276 from gsomlo/gls-rocket-map
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cpu/rocket: swap main_mem and io regions
2019-10-09 21:25:57 +02:00
f8f643a02f
cpu/rocket: swap main_mem and io regions
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The total size of RAM (main_mem) can be expected to vary significantly,
and often exceed the size needed for MMIO allocations by a large margin.
As such, place Rocket's MMIO (io regions) below 0x8000_0000, and start
the RAM (main_mem) at 0x8000_0000, with nothing above it to limit its
future growth.
Also, bump the pre-built Rocket verilog submodule to an updated version,
which also comes with matching changes to the way MMIO and RAM accesses
are mapped and routed to their respective AXI interfaces.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-09 14:25:41 -04:00
b627a8fe71
cpu: add default io_regions to CPUNone (all address range can be used as IO)
2019-10-09 12:06:21 +02:00
cc245fc8ec
Merge pull request #275 from pcotret/patch-1
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Update README (related to issue #273 )
2019-10-09 11:20:50 +02:00
a6b3aa3c62
soc_core: improve check_io_region error message
2019-10-09 10:47:19 +02:00
dc656d48c2
targets/sim: switch from shadow_base to io_regions
2019-10-09 10:38:22 +02:00
10146abf0a
cpu/rocket: move csr to IO region
2019-10-09 10:24:01 +02:00
Florent Kermarrec
Gabriel Somlo
Konrad Beckmann
Jan Kowalewski
Tim Ansell
Martin Cornil