Commit Graph

160 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 8c335d66fd framebuffer: fix alpha blending 2013-05-11 09:21:12 +02:00
Sebastien Bourdeauducq e96b027dee Framebuffer mixing 2013-05-10 21:03:55 +02:00
Sebastien Bourdeauducq 3ab83fb693 framebuffer: reorganize in preparation for mixer 2013-05-09 19:23:22 +02:00
Sebastien Bourdeauducq 06064d33aa dvisampler/dma: better 8:8:8 -> 10:10:10 conversion 2013-05-09 11:27:24 +02:00
Sebastien Bourdeauducq fe87221d2b dvisampler/dma: reverse slot allocation order 2013-05-09 10:51:50 +02:00
Sebastien Bourdeauducq 2df4ff0ad9 dvisampler/dma: fix interrupt generation 2013-05-09 10:51:34 +02:00
Sebastien Bourdeauducq d685ed21fc dvisampler/dma: bugfixes 2013-05-08 22:50:40 +02:00
Sebastien Bourdeauducq 29efa85dec dvisampler: new DMA engine (buggy) 2013-05-08 22:31:01 +02:00
Sebastien Bourdeauducq 8e76c960d9 timer, uart: EventSourceLevel -> EventSourceProcess 2013-05-08 18:11:42 +02:00
Sebastien Bourdeauducq e2d15b169a dvisampler: mostly working, very basic and slightly buggy DMA 2013-05-06 09:58:12 +02:00
Sebastien Bourdeauducq d05f3d22e0 chansync: bugfix 2013-05-05 15:07:57 +02:00
Sebastien Bourdeauducq d175e01876 dvisampler: connect sync polarity detection 2013-05-05 12:58:53 +02:00
Sebastien Bourdeauducq cb008a061c dvisampler/chansync: fix FIFO width 2013-05-05 12:58:24 +02:00
Sebastien Bourdeauducq ea20b74ed1 dvisampler/resdetection: use DE instead of hsync 2013-05-05 11:54:36 +02:00
Sebastien Bourdeauducq e3e1dcd547 dvisampler: add sync polarity detection module (thanks Lars for suggestions) 2013-05-05 11:53:38 +02:00
Sebastien Bourdeauducq 71e3bba228 dvisampler/decoding: hold C when DE=1 2013-05-05 11:51:48 +02:00
Sebastien Bourdeauducq 4259699d78 dvisampler: add RawDVISampler 2013-05-04 20:40:21 +02:00
Sebastien Bourdeauducq 63073319b0 dvisampler/datacapture: swap bit pairs 2013-05-04 20:38:50 +02:00
Sebastien Bourdeauducq 8222ee7f46 framebuffer: use DMA controller from Migen 2013-04-30 18:55:35 +02:00
Sebastien Bourdeauducq 43ac5c8471 Remove undriven reset signals 2013-04-25 20:19:49 +02:00
Sebastien Bourdeauducq 4ff1175dcf Use the Migen asynchronous FIFO 2013-04-25 19:43:26 +02:00
Sebastien Bourdeauducq 117b3b8ec7 adc: double-register asynchronous inputs 2013-04-19 12:32:12 +02:00
Werner Almesberger 0dca526a85 milkymist/adc/__init__.py: CounterADC - simple counter-based ADC
This is a revised version of the counter-based ADC.
2013-04-19 12:29:17 +02:00
Sebastien Bourdeauducq b018fcedc4 dvisampler/chansync: set synced to 0 when control tokens do not arrive at the same time 2013-04-16 22:21:03 +02:00
Sebastien Bourdeauducq 0d21711c1b dvisampler/chansync: use Record.raw_bits() 2013-04-14 17:06:29 +02:00
Sebastien Bourdeauducq 8914969760 dvisampler/clocking: insert DCM_CLKGEN before PLL 2013-04-14 16:53:19 +02:00
Werner Almesberger 7a6e56492c edid.py: sample SCL only every 64 clock cycles, to avoid bouncing
Possibly due to SCL rising fairly slowly (in the 0.5-1 us range),
bouncing has been observed while crossing the "forbidden" region
between Vil(max) and Vih(min).

By lowering the sample rate from once per system clock to once
every 64 clock cycles, we make sure we sample at most once during
the bounce interval and thus never see a false edge. (Although we
may see a rising edge one sample time late, which is perfectly
harmless.)
2013-04-12 22:48:46 +02:00
Sebastien Bourdeauducq 950d3a4469 framebuffer: use new flow API 2013-04-10 21:34:15 +02:00
Sebastien Bourdeauducq 3be20f6ae4 dfii: adapt to new Record API 2013-04-02 00:15:42 +02:00
Sebastien Bourdeauducq 4f4f260e76 Convert to new CSR API 2013-03-30 17:28:15 +01:00
Sebastien Bourdeauducq caa19f9ab2 framebuffer: larger counters 2013-03-29 17:15:11 +01:00
Sebastien Bourdeauducq 854c0461b4 framebuffer: process two pixels per system clock cycle 2013-03-28 20:46:16 +01:00
Sebastien Bourdeauducq 8fd092ca12 crg: support VGA pixel clock reprogramming 2013-03-28 19:07:17 +01:00
Sebastien Bourdeauducq 1e860c7472 Use new Mibuild generic_platform API 2013-03-26 17:57:17 +01:00
Sebastien Bourdeauducq 1045d64e6e framebuffer: RGBA -> ARGB 2013-03-25 18:32:25 +01:00
Sebastien Bourdeauducq 8ee6dab4f9 fb: better ordering of pixels within ASMI words 2013-03-25 15:56:54 +01:00
Sebastien Bourdeauducq 1333367de8 dvisampler: add resolution detection 2013-03-24 00:45:29 +01:00
Sebastien Bourdeauducq ee5bfd4d3d dvisampler/charsync: report position 2013-03-24 00:44:50 +01:00
Sebastien Bourdeauducq 99f9ffa7e8 dvisampler/decoding: set C to 0 during data 2013-03-24 00:44:19 +01:00
Sebastien Bourdeauducq fb9a2788e8 dvisampler/charsync: fix found_control signal 2013-03-24 00:43:22 +01:00
Sebastien Bourdeauducq e06585d9fe dvisampler: clean up EDID data 2013-03-23 13:48:40 +01:00
Sebastien Bourdeauducq 34b8388b45 dvisampler: decode before channel sync 2013-03-22 23:49:25 +01:00
Sebastien Bourdeauducq 037625886d dvisampler: decoding 2013-03-22 21:28:17 +01:00
Sebastien Bourdeauducq d65941d6cc dvisampler: channel synchronization 2013-03-22 18:37:10 +01:00
Sebastien Bourdeauducq 515cdb2bd8 dvisampler: character synchronization 2013-03-21 22:56:13 +01:00
Sebastien Bourdeauducq 7c4ca4fd66 dvisampler/datacapture: deserialize to 10 bits 2013-03-21 19:06:15 +01:00
Sebastien Bourdeauducq fa2331e084 dvisampler/clocking: generate pix reset 2013-03-21 19:02:04 +01:00
Sebastien Bourdeauducq 0a14c3714b dvisampler: software controlled phase detector 2013-03-21 00:46:29 +01:00
Sebastien Bourdeauducq 28cb97068c dvisampler/clocking: proper pix5x reset synchronization 2013-03-18 20:31:59 +01:00
Sebastien Bourdeauducq 5126f616fb dvisampler: use pix5x as IODELAY clock 2013-03-18 19:03:17 +01:00