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Author SHA1 Message Date
Sebastien Bourdeauducq
1857ec6c32 fhdl/namer: support ClockSignal and ResetSignal. Closes #24 2015-09-22 14:30:16 +08:00
Rohit Kumar Singh
71993edae4 Add init file in sdram/phy dir 
Without __init__.py file, when using setup.py, setuptools' find_package() function does not find the files in sdram/phy package. Hence .egg file entirely misses sdram/phy directory

More info here: https://bitbucket.org/pypa/setuptools/issues/97
 2015-09-21 23:46:16 +08:00
Sebastien Bourdeauducq
2c1553fea2 sim: insert resets, support ClockSignal and ResetSignal 2015-09-21 22:13:36 +08:00
Sebastien Bourdeauducq
99af825a5a sim: drive clock signals 2015-09-21 21:53:41 +08:00
Sebastien Bourdeauducq
a67b4baa0c sim: VCD output support 2015-09-21 21:20:31 +08:00
Sebastien Bourdeauducq
34ce6b077f verilog: remove unneeded import 2015-09-21 21:19:58 +08:00
Sebastien Bourdeauducq
b8647a161d doc: minor edits 2015-09-21 21:19:39 +08:00
Florent Kermarrec
b2a4eead0c uart/software: remove litescope dependency 2015-09-21 09:04:59 +02:00
Tim 'mithro' Ansell
bc1450e4f2 Adding --help option to flterm. 2015-09-21 11:02:36 +08:00
Sebastien Bourdeauducq
2ac748aef2 doc: remove spurious file 2015-09-20 16:13:08 +08:00
Sebastien Bourdeauducq
74b0cfc83b doc: remove outdated or moved parts, cleanup 2015-09-20 16:10:40 +08:00
Sebastien Bourdeauducq
1767eef9cb fhdl/visit: support Constant 2015-09-20 16:10:17 +08:00
Sebastien Bourdeauducq
87a8531952 travis: VPI is not there for now 2015-09-20 15:12:04 +08:00
Sebastien Bourdeauducq
7f767095ec sim: support generators yielding statements 2015-09-20 15:04:15 +08:00
Sebastien Bourdeauducq
320dffb4ac sim: memory access from generators 2015-09-20 14:52:26 +08:00
Sebastien Bourdeauducq
59802bec76 fhdl/structure: add missing init 2015-09-20 14:46:30 +08:00
Sebastien Bourdeauducq
8bbfaa01fc sim: memory support 2015-09-19 23:21:46 +08:00
Sebastien Bourdeauducq
1861ae9d01 fhdl/specials: MemoryPort.clock should always be a ClockSignal 2015-09-19 23:21:24 +08:00
Sebastien Bourdeauducq
262fd50677 fhdl/simplify: add MemoryToArray 2015-09-19 23:20:57 +08:00
Sebastien Bourdeauducq
944a0b0480 test/fifo: convert to new API 2015-09-19 23:20:30 +08:00
Sebastien Bourdeauducq
dcf4f7fef3 genlib/fifo: add missing import 2015-09-19 23:20:19 +08:00
Sebastien Bourdeauducq
9420aabc0d sim: support arrays, and cat+slice in assignment target 2015-09-19 14:56:26 +08:00
Sebastien Bourdeauducq
ef92aa35f2 Merge branch 'master' of github.com:m-labs/migen 2015-09-19 12:22:47 +08:00
Florent Kermarrec
563231fdfb migen/genlib/cdc: fix BusSynchronizer 
ping/pong token can be lost when:
- source clock domain starts before destination clock domain.
- a clock domain stops.

This fix add a timeout to detect such situation and create another token.
 2015-09-19 12:21:54 +08:00
Florent Kermarrec
210ba91d58 migen/genlib/cdc: fix BusSynchronizer 
ping/pong token can be lost when:
- source clock domain starts before destination clock domain.
- a clock domain stops.

This fix add a timeout to detect such situation and create another token.
 2015-09-19 12:18:39 +08:00
Sebastien Bourdeauducq
bfcc8f9661 sim: remove unneeded import 2015-09-19 12:18:20 +08:00
Sebastien Bourdeauducq
84f98b4632 genlib/CRG: fix variable name conflict 2015-09-19 11:18:44 +08:00
Sebastien Bourdeauducq
0a55ef5bc3 test: add divider 2015-09-18 11:07:14 +08:00
Florent Kermarrec
e4329c739c actorlib/structuring: fix Pack in packetized mode 
Params need to be registered for the case when eop appears before the end of the pack cycle.
 2015-09-18 02:28:02 +02:00
Sebastien Bourdeauducq
ec1d4edf84 sim: support Case 2015-09-17 17:25:06 +08:00
Sebastien Bourdeauducq
9d3fd50950 sim: variables are deprecated 2015-09-17 17:24:57 +08:00
Sebastien Bourdeauducq
2688d66ea1 sim: fix comb evaluation 2015-09-17 17:24:20 +08:00
Sebastien Bourdeauducq
049a8f082a test/size: do not test removed functions 2015-09-17 17:23:19 +08:00
Sebastien Bourdeauducq
4a3a1bc5b0 test/coding: use new API 2015-09-17 17:22:59 +08:00
Sebastien Bourdeauducq
12cd390c0b genlib/misc: add missing import 2015-09-17 17:22:44 +08:00
Sebastien Bourdeauducq
776579f0d7 fhdl/structure: all case statements should be lists 2015-09-17 17:22:24 +08:00
Sebastien Bourdeauducq
bcf62997f6 fhdl/bitcontainer: remove fiter 2015-09-17 17:22:03 +08:00
Sebastien Bourdeauducq
c2109f8f81 minor bugfixes 2015-09-17 15:20:27 +08:00
Sebastien Bourdeauducq
6e08df75ee sim: support eval of slice, cat and mux 2015-09-17 14:39:36 +08:00
Sebastien Bourdeauducq
9dd3200ba2 fhdl/structure: fix namespace pollution 2015-09-17 14:39:17 +08:00
Sebastien Bourdeauducq
6569c516a1 test: bit reverse 2015-09-17 14:38:55 +08:00
Sebastien Bourdeauducq
0a92e346d3 fhdl/bitcontainer: remove fslice and freversed 2015-09-17 14:38:33 +08:00
Sebastien Bourdeauducq
fd88b9b8a3 test/constant: use new API 2015-09-17 11:08:40 +08:00
Robert Jordens
74c9159a01 add unittests for Constant 2015-09-17 11:06:04 +08:00
Sebastien Bourdeauducq
0b9c6720d8 doc: Constant 2015-09-17 11:05:57 +08:00
Sebastien Bourdeauducq
f5ab734bdf fhdl/verilog: fix case value sort 2015-09-17 08:03:48 +08:00
Sebastien Bourdeauducq
e940c6d9b9 fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem 2015-09-15 12:38:02 +08:00
Sebastien Bourdeauducq
42afba2bbc fhdl/decorators: remove traces of deprecated API 2015-09-12 19:44:35 +08:00
Sebastien Bourdeauducq
eb921fb957 genlib: remove reverse_bytes, FlipFlop, Counter 2015-09-12 19:40:29 +08:00
Sebastien Bourdeauducq
9667d61e84 genlib: cleanup CRG 2015-09-12 19:40:07 +08:00