Florent Kermarrec
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92a6169d2a
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build/sim: add coverage parameter to enable code coverage
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2018-12-09 08:10:50 +01:00 |
|
Florent Kermarrec
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0c687bc29e
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soc/interconnect/stream: add support for buffered async fifo
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2018-12-08 01:24:08 +01:00 |
|
Florent Kermarrec
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bf3b4eec34
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gen: integrate migen changes
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2018-12-04 21:06:51 +01:00 |
|
Florent Kermarrec
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96527b5a3a
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soc/interconnect/stream/gearbox: remove bit reversing by changing words order
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2018-11-30 23:12:30 +01:00 |
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Florent Kermarrec
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1c8c2426b9
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Merge branch 'master' of http://github.com/enjoy-digital/litex
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2018-11-27 17:45:07 +01:00 |
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Florent Kermarrec
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8887fc24c4
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build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build).
Old version of Vivado don't have XPM support and enable it break the build.
Enabling XPM is only useful in some cases, we can do it manually.
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2018-11-27 17:42:39 +01:00 |
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enjoy-digital
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cc4ba65659
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Merge pull request #130 from jfng/master
litex_sim: add --trace argument
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2018-11-27 17:35:03 +01:00 |
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Florent Kermarrec
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ec46beeb47
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targets/ulx3s, versa_ecp5: use ECP5PLL
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2018-11-27 17:31:53 +01:00 |
Jean-François Nguyen
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71398e0155
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litex_sim: add --trace argument
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2018-11-27 17:26:32 +01:00 |
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Florent Kermarrec
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18048eb454
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cores/clock: test and fix ECP5PLL, phase still not implemented.
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2018-11-27 17:24:22 +01:00 |
|
Florent Kermarrec
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20dd95c541
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boards/platforms/ulx3s: add gpios 0-3
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2018-11-27 14:15:35 +01:00 |
|
Florent Kermarrec
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909cff1940
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bios/sdram: flush l2 cache only when present
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2018-11-26 18:37:45 +01:00 |
|
Florent Kermarrec
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2ad83778bf
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bios: allow testing main_ram at init when using an external controller
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2018-11-26 15:21:00 +01:00 |
|
Florent Kermarrec
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cdfe0454bb
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build/microsemi/libero_soc: small cleanup
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2018-11-26 11:35:06 +01:00 |
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enjoy-digital
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4592e3235b
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Merge pull request #128 from mithro/small-fix
Two small fixes
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2018-11-26 09:48:10 +01:00 |
Tim 'mithro' Ansell
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4f565c5179
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stream.Endpoint: Pass extra arguments to superclass.
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2018-11-25 12:57:11 -08:00 |
|
Tim 'mithro' Ansell
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3b9e4c4df6
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wishbone.SRAM: Support non-32bit wishbone widths.
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2018-11-25 12:56:37 -08:00 |
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Florent Kermarrec
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515c06219a
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cores/clock: add ECP5PLL
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2018-11-24 00:47:38 +01:00 |
|
Florent Kermarrec
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7623b5dd96
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soc/interconnect/stream/gearbox: inverse bit order
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2018-11-23 18:34:24 +01:00 |
|
Florent Kermarrec
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d32e393033
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soc/cores/spi_flash: add missing endianness parameter
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2018-11-23 18:33:53 +01:00 |
|
Florent Kermarrec
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c954943e02
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platforms/avalanche: add IOStandard on ddram pins
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2018-11-23 12:47:45 +01:00 |
|
Florent Kermarrec
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09a1cda943
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build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification
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2018-11-23 09:30:13 +01:00 |
|
Florent Kermarrec
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a98e1ad689
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build/microsemi/libero_soc: add additional_timing_constraints
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2018-11-23 09:04:42 +01:00 |
|
Florent Kermarrec
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b166882308
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build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper
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2018-11-23 08:26:31 +01:00 |
|
Florent Kermarrec
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9df75d7d63
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platforms/avalanche: add package/speed to platform.device
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2018-11-23 08:24:29 +01:00 |
|
Florent Kermarrec
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953b1f70df
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build/microsemi/libero_soc: remove previous impl directory if exists
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2018-11-23 08:11:57 +01:00 |
|
Florent Kermarrec
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18d513a146
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build/microsemi/libero_soc: give better names to pdc files: io/fp
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2018-11-23 08:03:55 +01:00 |
|
Florent Kermarrec
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4f092dbe35
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build/microsemi/libero_soc: add additional_constraints
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2018-11-22 18:40:19 +01:00 |
|
Florent Kermarrec
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206c9a4697
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platforms/avalanche: fix ddram dq7
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2018-11-22 18:13:33 +01:00 |
|
Florent Kermarrec
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f003407776
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build/microsemi/libero_soc: add {} around port name.
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2018-11-22 17:37:03 +01:00 |
|
Florent Kermarrec
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beeca856e5
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utils/litex_read_verilog: fix generated indent on instance
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2018-11-22 17:33:46 +01:00 |
|
Florent Kermarrec
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1fe7d09fb5
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soc/integration/soc_core: add csr_map_update function
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2018-11-21 08:39:52 +01:00 |
|
Tim Ansell
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ab799f7bd7
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Merge pull request #127 from cr1901/picorv32-data
libbase/crt0-picorv32: Add support for .data sections.
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2018-11-20 21:15:50 -08:00 |
William D. Jones
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89c702187a
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libbase/crt0-picorv32: Add support for .data sections.
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2018-11-21 00:13:13 -05:00 |
|
Florent Kermarrec
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80bdae0e55
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build/sim/verilator: add trace parameter to enable tracer
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2018-11-20 18:54:22 +01:00 |
|
Florent Kermarrec
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7359a99bf9
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soc_core: convert cpu_type="None" string to None
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2018-11-20 17:45:11 +01:00 |
|
Florent Kermarrec
|
5805d63013
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build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route
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2018-11-19 16:36:30 +01:00 |
|
Florent Kermarrec
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85f7666207
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build/microsemi/common: add async reset synchronizer (using DFN1P0)
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2018-11-19 15:35:59 +01:00 |
|
Florent Kermarrec
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e3c6bd5846
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build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools
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2018-11-19 12:50:07 +01:00 |
|
Florent Kermarrec
|
4c966114f8
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build/microsemi/libero_soc: add timing constraints support
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2018-11-19 09:40:16 +01:00 |
|
Florent Kermarrec
|
60faae490a
|
boards/platforms/avalanche: fix swapped serial pins
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2018-11-19 08:45:55 +01:00 |
|
Florent Kermarrec
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52396add5d
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boards/platforms/avalanche: rename rst to rst_n (active low reset)
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2018-11-19 08:14:46 +01:00 |
|
Florent Kermarrec
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8e07e1a099
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build/microsemi/libero_soc: associate .pdc to place and route tool.
For constraint to be applied, we also to associate them with the tool that will use it.
|
2018-11-19 08:07:36 +01:00 |
|
Florent Kermarrec
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5137c2bf88
|
test/test_targets: update
|
2018-11-17 17:36:57 +01:00 |
|
Florent Kermarrec
|
a5ed42ec68
|
soc/interconnect/stream: add Gearbox
|
2018-11-17 17:29:45 +01:00 |
|
Florent Kermarrec
|
11d536dc4d
|
test: remove test_bitslip (integrated in migen)
|
2018-11-17 17:29:09 +01:00 |
|
Florent Kermarrec
|
a25645afa6
|
utils: add litex_read_verilog utility
generate Migen's modules from verilog files
|
2018-11-16 16:09:44 +01:00 |
|
Florent Kermarrec
|
a538d36268
|
create utils directory and move the litex utils to it
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2018-11-16 14:37:19 +01:00 |
|
Florent Kermarrec
|
45ec78e93a
|
build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board.
|
2018-11-16 12:19:03 +01:00 |
|
Florent Kermarrec
|
4cb6583b4e
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build: add microsemi template for polarfire fpgas support
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2018-11-15 18:21:41 +01:00 |