3c70c83f9b
cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.
2020-05-01 12:41:14 +02:00
74dc444b02
bios: add auto completion for commands
2020-05-01 12:12:35 +02:00
fc2b8226c5
bios: switch command handler to a modular format
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Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
2020-05-01 12:12:35 +02:00
86cab3d362
bios: move helper functions to their own file
2020-05-01 12:12:35 +02:00
bc5a1986e2
bios: add terminal history
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Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
2020-05-01 12:12:07 +02:00
e764eabda1
builder: add a parameter to pass options to BIOS Makefile
2020-05-01 12:10:50 +02:00
bb70a2325a
cpu/software: move CPU specific software from the BIOS to the CPU directories.
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This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.
The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
2020-05-01 11:04:54 +02:00
0abc7d4f0b
cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository.
2020-05-01 11:03:07 +02:00
b82b3b7ecf
integration/soc: rename usb_cdc to usb_acm.
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As discussed on Discord recently.
2020-04-30 21:45:53 +02:00
0a1afbf66f
litex/__init__.py: remove retro-compat > 6 months old.
2020-04-30 21:31:58 +02:00
3531a64173
soc: allow passing custom CPU class to SoC.
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Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
2020-04-29 20:12:23 +02:00
64b505156e
Add RDIMM side-B inversion support
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:28:53 +01:00
90a6343df1
Merge pull request #488 from enjoy-digital/python3.5
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travis: add back test on python3.5 (python3.6 is recommended but we c…
2020-04-29 08:48:06 +02:00
9941e4c16b
travis: add back test on python3.5 (python3.6 is recommended but we can try to keep 3.5 compatibility until we have good reason to no longer support it).
2020-04-29 08:43:02 +02:00
83f4dcb2c6
Added `imac` config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv
2020-04-28 22:27:35 +02:00
ac1e968351
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-04-28 22:25:57 +02:00
a11f1c39b7
Removed erase flag and made progress output less noisy
2020-04-28 22:22:33 +02:00
855d614e5d
Merge pull request #481 from betrusted-io/unfstringify
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propose patch to not break litex for python 3.5
2020-04-28 19:05:08 +02:00
17b766546b
propose patch to not break litex for python 3.5
2020-04-29 00:34:19 +08:00
00f973ea35
spi_flash: extend non-bitbanged flash support
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This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.
It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
2020-04-28 15:02:55 +02:00
56aa7897df
create first release, add CHANGES and note about Python modules in README.
2020-04-28 11:36:44 +02:00
6d0896de1d
cpu/serv: switch to pythondata package instead of local git clone.
2020-04-28 10:34:39 +02:00
1b06926882
README: update Python minimal version to 3.6.
2020-04-28 09:02:59 +02:00
ff61b1f6fa
litex_setup: disable automatic clone of BlackParrot/Microwatt CPUs, reorder LiteX data.
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The support is not fully finished, so let the user install the pythondata for these CPUs manually with pip.
2020-04-28 09:01:06 +02:00
4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py
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Converting LiteX to use Python modules.
2020-04-28 08:34:19 +02:00
5ef869b9eb
soc/cpu: add memory_buses to cpus and use them in add_sdram.
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This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
2020-04-27 23:53:52 +02:00
467fee3e23
soc/cpu: rename cpu.buses to cpu.periph_buses.
2020-04-27 23:08:15 +02:00
317ea7edd1
Merge branch 'master' into litex-sm2py
2020-04-27 22:24:10 +02:00
05815c4ecc
Merge pull request #477 from shuffle2/patch-1
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diamond: fix include paths
2020-04-27 21:07:27 +02:00
f71014b9fb
diamond: fix include paths
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include paths given via tcl script need semicolon separators and forward slash as directory separator (even on windows)
2020-04-27 11:14:18 -07:00
4dece4ce24
soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case).
2020-04-27 19:06:16 +02:00
c5ef9c7356
Merge pull request #473 from fjullien/memusage
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bios: print memory usage
2020-04-27 18:24:43 +02:00
3892d7a90a
bios: print memory usage
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Print memory usage during the compilation of bios.elf.
2020-04-27 16:33:34 +02:00
9460e048ec
tools/litex_sim: use similar analyzer configuration than wiki.
2020-04-27 16:10:41 +02:00
443cc72d0a
Merge pull request #476 from enjoy-digital/serv
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Add SERV support (The SErial RISC-V CPU)
2020-04-27 13:59:28 +02:00
1d1a4ecd28
software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning.
2020-04-27 13:47:13 +02:00
fb9e369a19
serv: connect reset.
2020-04-27 13:26:45 +02:00
c4c891dec5
build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis).
2020-04-27 13:17:53 +02:00
192849f0b6
Merge pull request #475 from gregdavill/read_verilog_defer
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build/trellis: add verilog_read -defer option to yosys script
2020-04-27 13:13:37 +02:00
642c4b3036
build/trellis: add verilog_read -defer option to yosys script
2020-04-27 20:10:25 +09:30
71778ad226
serv: update copyrights (Greg Davill found the typos/issues).
2020-04-27 10:27:44 +02:00
1f9db583fd
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
2020-04-26 21:05:47 +02:00
2efd939d06
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
2020-04-26 16:26:57 +02:00
96e7e6e89a
bios/sdram: reduce number of scan loops during cdly scan to speed it up.
2020-04-25 12:51:33 +02:00
43e1a5d67d
targets/kcu105: use cmd_latency=1.
2020-04-25 12:12:27 +02:00
85a059bf77
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
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We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
2020-04-25 12:11:10 +02:00
038e1bc048
targets/kc705: manual DDRPHY_CMD_DELAY no longer needed.
2020-04-25 11:03:04 +02:00
aaed4b9475
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
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Working on KC705 that previously required manual adjustment.
2020-04-25 11:00:21 +02:00
33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration
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bios/sdram: add automatic cdly calibration during write leveling
2020-04-25 09:59:08 +02:00
4608bd1864
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings
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litex_sim: add option to create SDRAM module from SPD data
2020-04-25 08:27:00 +02:00
Florent Kermarrec
Franck Jullien
David Shah
Ilya Epifanov
bunnie
Jakub Cebulski
shuffle2
Greg Davill