Commit Graph

269 Commits

Author SHA1 Message Date
Florent Kermarrec 67702f25ab migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb) 2015-04-24 12:54:08 +02:00
Florent Kermarrec bc30fc57e7 migen/fhdl: give explicit names to syntax specialization when asic_syntax is used 2015-04-24 12:14:14 +02:00
Guy Hutchison 28dde1e38f fhdl/verilog: add flag to produce ASIC-friendly output 2015-04-21 09:52:14 +08:00
Florent Kermarrec 3f15699964 revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue) 2015-04-13 21:47:55 +02:00
Florent Kermarrec f97d7ff44c global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
Florent Kermarrec 37ef9b6f3a global: pep8 (E231) 2015-04-13 20:50:03 +02:00
Florent Kermarrec 1051878f4c global: pep8 (E302) 2015-04-13 20:45:35 +02:00
Florent Kermarrec 17e5249be0 global: pep8 (replace tabs with spaces) 2015-04-13 20:07:07 +02:00
Florent Kermarrec ff23960657 fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
2015-04-10 17:18:07 +02:00
Sebastien Bourdeauducq e1702c422c introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
Robert Jordens 8798ee8d73 decorators: fix stacklevel, export in std 2015-04-05 18:47:45 +08:00
Robert Jordens f26ad97624 decorators: fix ControlInserter 2015-04-05 14:44:03 +08:00
Sebastien Bourdeauducq db76defa2a fhdl/visit: remove TransformModule 2015-04-04 20:12:22 +08:00
Robert Jordens e702fb7727 decorators: fix class/instance logic 2015-04-04 19:16:58 +08:00
Robert Jordens 4091af69fd fhdl/decorators: make the transform logic more idiomatic
* the transformers work on classes and instances.
  you can now do just do:

    @ResetInserter()
    @ClockDomainRenamer({"sys": "new"})
    class Foo(Module):
        pass

  or:

    a = ResetInserter()(FooModule())

* the old usage semantics still work
* the old DecorateModule is deprecated,
  ModuleDecorator has been refactored into ModuleTransformer
  (because it not only decorates things)
2015-04-04 19:16:50 +08:00
Sebastien Bourdeauducq c169f0b189 Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
This reverts commit f03aa76292.
2015-03-30 19:41:16 +08:00
Sebastien Bourdeauducq dc88295338 Revert "migen/fhdl: pass fdict filename --> contents to specials"
This reverts commit ea04947519.
2015-03-30 19:41:13 +08:00
Sebastien Bourdeauducq b1c811a3d1 Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"
This reverts commit 95cfc444e6.
2015-03-30 19:41:04 +08:00
Florent Kermarrec 95cfc444e6 migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method 2015-03-30 11:37:59 +02:00
Florent Kermarrec ea04947519 migen/fhdl: pass fdict filename --> contents to specials 2015-03-30 11:37:57 +02:00
Florent Kermarrec f03aa76292 migen: create VerilogConvert and EDIFConvert classes and return it with convert functions 2015-03-30 11:37:55 +02:00
Sebastien Bourdeauducq 7fa1cd72a8 fhdl/verilog: fix dummy signal initial event 2015-03-19 00:24:30 +01:00
Florent Kermarrec 5a9afee234 fhdl/specials/memory: use $readmemh to initialize memories 2015-03-18 15:27:01 +01:00
Florent Kermarrec c0fb0ef600 fhdl/verilog: change the way we initialize reg: reg name = init_value;
This allows simplifications (init in _printsync and _printinit no longer needed)
2015-03-18 15:05:26 +01:00
Florent Kermarrec ea9c1b8e69 fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"
This probably breaks simulation with Icarus Verilog (and others simulators?)
2015-03-18 14:59:22 +01:00
Sebastien Bourdeauducq bdc47b205a Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)"
This breaks simulations, and we will try to use the "reg name = value" syntax instead.

This reverts commit e946f6e453.
2015-03-18 12:08:25 +01:00
Florent Kermarrec b7d7fe1a4c fhdl/special: add optional synthesis directive (needed by Synplify Pro) 2015-03-17 14:59:05 +01:00
Florent Kermarrec 9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
2015-03-17 00:40:26 +01:00
Florent Kermarrec e946f6e453 fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it) 2015-03-16 23:47:07 +01:00
Sebastien Bourdeauducq c824379878 fhdl/visit: fix TransformModule 2015-03-14 17:45:11 +01:00
Florent Kermarrec ebcea3c000 fhdl/module: use r.append() in _collect_submodules 2015-03-09 19:45:02 +01:00
Florent Kermarrec ee1091f491 fhdl/module: avoid flushing self._submodules and create do_exit. 2015-03-09 17:17:21 +01:00
Florent Kermarrec 2175a79c03 fhdl/std: add FinalizeError import 2015-01-23 00:23:41 +08:00
Sebastien Bourdeauducq 5801e5746b fhdl/tools: do not attempt to rename sync clock domain if it does not exist 2014-11-21 14:51:05 -08:00
Sebastien Bourdeauducq a4782899f6 fhdl/verilog: fix tristate to instance connection 2014-10-29 18:18:17 +08:00
Yann Sionneau 286092b62e Raise exception when not using correct boolean operators 2014-10-27 19:40:22 +08:00
Florent Kermarrec dbaeaf7833 remove trailing whitespaces 2014-10-17 17:08:46 +08:00
Robert Jordens bd232f3f61 fhdl.structure: do not permit clock domain names that start with numbers 2014-08-18 11:01:56 +08:00
Robert Jordens ac2e961618 fhdl.structure: remove unused imports 2014-08-18 11:01:56 +08:00
Robert Jordens 6036fffef2 Signal.__getitem__: raise TypeError and IndexError when appropriate 2014-08-18 11:01:56 +08:00
Robert Jordens b3d69913cd Signal.like: pass kwargs 2014-08-18 11:01:56 +08:00
Robert Jordens 44c6e524ba migen.fhdl.structure: add Signal.like(other)
This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
2014-07-24 23:52:59 -06:00
Sebastien Bourdeauducq 29ed3918cc fhdl: forbid zero-length signals 2014-04-18 15:01:50 +02:00
Sebastien Bourdeauducq 90f0dfad63 Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator 2014-01-27 23:58:46 +01:00
Sebastien Bourdeauducq 63c1d7e4b7 New simulation API 2014-01-26 22:19:43 +01:00
Robert Jordens be1c8551d2 migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime) 2013-12-17 18:40:49 +01:00
Sebastien Bourdeauducq a20688f777 fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems 2013-12-13 00:02:50 +01:00
Sebastien Bourdeauducq adda930c68 fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs 2013-12-12 17:37:31 +01:00
Sebastien Bourdeauducq c13fe1bc63 specials/Memory: allow for more flexibility in memory port signals 2013-12-12 17:36:17 +01:00
Sebastien Bourdeauducq 135a4fea25 fhdl/verilog: fix representation of negative integers
Give the explicit two's complement representation for the given bit width.

This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
2013-12-11 22:26:10 +01:00