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8550 Commits

Author SHA1 Message Date
Florent Kermarrec 727d898a6c software/libliteeth: Update/Fix compilation with picolibc. 2021-09-27 18:54:28 +02:00
Florent Kermarrec 54623dbe26 litex_setup: Update picolibc url (now on litex-hub). 2021-09-27 18:15:10 +02:00
enjoy-digital 7119dd8098
Merge pull request #1023 from lschuermann/dev/litex-sim-gmii-xgmii 
litex_sim: add support for simulated GMII & XGMII, rewrite XGMII module
 2021-09-27 17:48:44 +02:00
enjoy-digital 87f7f3bc45
Merge branch 'master' into dev/litex-sim-gmii-xgmii 2021-09-27 17:47:26 +02:00
Florent Kermarrec 9ab82cacda soc/add_ethernet/etherbone: Fix conflicts/Update. 2021-09-27 17:43:39 +02:00
enjoy-digital 17abdfd12d
Merge pull request #1043 from enjoy-digital/rocket-remove-reset-inserter 
cpu/rocket/core: Remove ResetInserter on adapters.
 2021-09-27 16:34:46 +02:00
Florent Kermarrec 49f8652f91 ci: Install meson (now required by picolibc). 2021-09-27 16:19:56 +02:00
Florent Kermarrec 746d698b49 litex_setup.py: Revert LiteX url. 2021-09-27 16:15:16 +02:00
Florent Kermarrec 3d32ac3d2e software: Avoid libase renaming to libutils/libcomm and keep readchar/putsnonl retro-compatibility. 
We'll maybe do it but that's probably not the right time. We have to make
the picolibc switch as smooth as possible for users (and so avoid update
as much as possible).

In the long term, it would be good to provide a LiteX C SDK, so we'll make
eventual changes when doing this.
 2021-09-27 16:15:13 +02:00
Florent Kermarrec ae1d43b965 software/libc/Makefile: Use proper CFLAGS to avoid picolibc warnings and cleanup a bit Makefile. 2021-09-27 16:14:55 +02:00
enjoy-digital c0b54f0105
Merge pull request #976 from antmicro/libbase-replacement 
Replace libbase with picolibc
 2021-09-27 16:05:24 +02:00
Florent Kermarrec 944732aa19 soc/add_sdram: Also remove ResetInserter on axi.AXI2Wishbone. 2021-09-27 15:46:19 +02:00
Franck Jullien 06ff638f7a efinix: rgmii: fix, it's in a working state 2021-09-27 10:11:58 +02:00
Franck Jullien 1ea0797c82 efinix: ifacewriter: fix DRIVE_STRENGTH and REFCLK_FREQ 2021-09-27 10:11:00 +02:00
Florent Kermarrec ce0551b44a cpu/rocket/core: Remove ResetInserter on adapters. 
Previously, the SoCController was only reseting the CPU, which required adding
these ResetInserters. Now that the SoCController resets both CPU and peripherals
these ResetInserters are redundant and no longer useful.
 2021-09-27 09:05:46 +02:00
Franck Jullien 179a8018b3 efinix: RGMII phy should be operational (no tested) 
PLL infrastructure should be complete now.
We can also use DDIO input and outputs.
However, there is problem (bug) during P&R:

ERROR(1): [Line 52] Block auto_eth_tx_delayed_clk is
an output pad but sub-block 1 is not an output pad location.

Inderface Designer validation doesn't report any problem.
I have a test project with the same configuration (I compared
the reports for blocks configuration) and it works.
 2021-09-23 17:21:17 +02:00
enjoy-digital c43132f81f
Merge pull request #1040 from gsomlo/gls-rocket-smp 
Rocket SMP support
 2021-09-23 10:56:06 +02:00
Gabriel Somlo 07e47d9357 cpu/rocket: add quad-core (smp) variants 
- 4-core "full" (fpu-enabled) variants with double, quad mem. bus width
- 4-core "linux" (fpu-less) variant with single (64-bit) mem. bus width
 2021-09-22 16:59:04 -04:00
Gabriel Somlo 901b19828c cpu/rocket: include core count as per-variant parameter 
Repurpose (and rename to `CPU_SIZE_PARAMS`) the current
`AXI_DATA_WIDTHS` array. In addition to axi widths for
mem and mmio ports, also include each variant's number
of cores, to facilitate dynamically generated per-core
signals.
 2021-09-22 16:58:11 -04:00
Gabriel Somlo e6aaa40d2d cpu/rocket: bios support for SMP 2021-09-22 13:51:18 -04:00
Gabriel Somlo 2bc8124114 cpu/rocket: crt0, boot-helper: use temp. registers (cosmetic) 2021-09-22 13:51:18 -04:00
enjoy-digital 1d302c56da
Merge pull request #1041 from gsomlo/gls-vex-smp-fix 
cpu/vexriscv_smp/crt0.S: only boot core should run data_init
 2021-09-22 19:35:47 +02:00
Florent Kermarrec 60c6077c32 remote/comm_udp: Add padding bytes to Etherbone probe. 
Now required with LiteEth dropping exceeding payload.
 2021-09-22 16:52:08 +02:00
Gabriel Somlo 23b2ac2013 cpu/vexriscv_smp/crt0.S: only boot core should run data_init 
Also, no need for non-boot cores to `call smp_slave`, it's the
immediately following instruction for them already.
 2021-09-22 09:55:20 -04:00
Franck Jullien 109dbd1d62 efinity: small fixes 
- do not include *.vh files in project,
- add self.options to class EfinityToolchain
- remove unconditional call to self.ifacewriter.add_ddr_xml
 2021-09-22 09:53:27 +02:00
Franck Jullien b24475b07d Add an hacked no we memory for Efinix 
Efinity synthesizer cannot infer RAM blocks with write enable.
In order to workaround this (at least for the Litex SoC intergrated
RAM/ROM) a dirty modified Memory class has been created.

This class needs to be rewrite !
 2021-09-22 09:47:51 +02:00
Florent Kermarrec 027f7aa645 tools/litex_json2dts_linux: Fix typo. 2021-09-21 14:32:20 +02:00
Franck Jullien bd71dc663f efinix: more DDR work, still WIP 2021-09-21 14:23:36 +02:00
Franck Jullien b765bdf34e efinix: pll: allow output name to be changed 2021-09-21 14:23:00 +02:00
Franck Jullien 7a5f5a3682 efinix: remove redundant param in _build_xml 2021-09-21 14:22:17 +02:00
Florent Kermarrec 84f1afd6d4 tools/litex_json2dts_linux: Remove mem=/, init= and swiotlb= bootargs. 
Were not useful as pointed by @shenki and @stffrdhrn.
 2021-09-21 13:37:25 +02:00
enjoy-digital b1b1e92ad0
Merge pull request #1032 from stffrdhrn/json2dts-sdcard 
Json2dts sdcard booting
 2021-09-21 13:13:07 +02:00
Franck Jullien 24a920f2d1 efinix: add preliminary DDR support (WIP) 2021-09-21 10:58:54 +02:00
Andwer E Wilson 9f75c73d6b build/xilinx/common: Fix Ultrascale SDROutput/Input. 2021-09-21 10:30:36 +02:00
enjoy-digital 233f0fc5f4
Merge pull request #1039 from tcal-x/rm-response-ok 
Remove rsp_payload_response_ok from Vex/CFU hookup code.
 2021-09-21 09:43:15 +02:00
Florent Kermarrec 08779202f4 build/DDRTristate: Fix inconsistencies with SDRTristate (o/i swap). 2021-09-21 08:18:06 +02:00
Tim Callahan 1be449d72b Remove rsp_payload_response_ok from Vex/CFU hookup code. 
The port has already been removed from VexRiscv (issue #1036).

Signed-off-by: Tim Callahan <tcal@google.com>
 2021-09-20 15:02:51 -07:00
Florent Kermarrec 1e24fd87d1 cores/gpio: Simplify #1035. 2021-09-20 17:34:46 +02:00
enjoy-digital 6251474b39
Merge pull request #1035 from lschuermann/dev/litex-sim-gpio 
litex_sim: optionally add GPIOTristate core
 2021-09-20 17:21:29 +02:00
enjoy-digital 0daa86a8bb
Merge pull request #1038 from antmicro/crosslinknx-ddr-tristate 
build/lattice: add DDRTristate for Crosslink-NX
 2021-09-20 14:14:40 +02:00
Florent Kermarrec 49d8000d49 gowin/common: Add Differential Input/Output support. 2021-09-20 14:14:06 +02:00
Franck Jullien b9e99f576c efinix: use proper xml to create project file 2021-09-20 13:35:45 +02:00
Florent Kermarrec 9c373242af gowin: Add HyperRAM integration hack to match Gowin EDA expected pattern. 2021-09-20 11:47:32 +02:00
Maciej Kurc 6c0a758468 Added syn_useioff attribute support for Oxide toolchain and for the DDRTristate in Crosslink NX 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-20 11:02:01 +02:00
Franck Jullien efebefecea efinix: add PLL reset and locked pins 2021-09-20 10:42:27 +02:00
Franck Jullien a026dd8946 efinix: add AsyncResetSynchronizer 2021-09-20 10:41:59 +02:00
Franck Jullien 08be77caaf efinix: ifacewriter, enable design generation 2021-09-20 10:41:00 +02:00
Florent Kermarrec 5519d908e8 cores/video: Rename VideoECP5HDMIPHY to VideoHDMIPHY since in fact generic and can be used on other FPGAs (ex Tang Nano 4k). 2021-09-20 09:29:05 +02:00
Franck Jullien 106b1f29a7 efinix: fix programmer load_bitstream 2021-09-20 08:42:27 +02:00
Florent Kermarrec 4fe085cc1c cores/clock: Add initial GW1NSR's PLL support. 2021-09-20 08:39:25 +02:00