Sebastien Bourdeauducq
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a2c7ff4c0c
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sdramphy: initial K7 DDR3 support
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2014-08-08 21:28:26 +08:00 |
Florent Kermarrec
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293ac09673
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sdramphy/bios: make sdrrd/sdrwr generic
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2014-08-08 19:25:10 +08:00 |
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Sebastien Bourdeauducq
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cfc37a3fa5
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sdramphy/initsequence: rewrite DDR3 initialization sequence
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2014-08-08 19:15:05 +08:00 |
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Sebastien Bourdeauducq
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e8db842538
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s6ddrphy: fix DFI interface data width computation
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2014-08-08 19:14:15 +08:00 |
|
Sebastien Bourdeauducq
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efb2466c7e
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gensoc: add id for KC705
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2014-08-06 23:53:51 +08:00 |
|
Florent Kermarrec
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d1ff43faa7
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gensoc/cpuif: do not generate access functions for registers > 64 bits
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2014-08-04 22:38:19 +08:00 |
|
Sebastien Bourdeauducq
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213cb43ae5
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Keep only basic SoC designs in MiSoC
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2014-08-03 12:30:15 +08:00 |
|
Florent Kermarrec
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25b3aff6f1
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sdramphy: add init sequence for DDR3
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2014-07-31 10:29:32 +08:00 |
Yann Sionneau
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32171da46d
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Better UART baudrate generator, and testbench
This enables high speed (tested to 4Mbps) operation.
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2014-07-31 10:24:52 +08:00 |
|
Florent Kermarrec
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d4833cb3dc
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cpuif: remove limitations on csr data_width
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2014-06-28 17:39:55 +02:00 |
Robert Jordens
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81ed92d3b9
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spiflash: redundant slice
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2014-05-24 10:39:07 +02:00 |
|
Florent Kermarrec
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f4c0648289
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gensdrphy: fix dm generation
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2014-05-21 21:16:06 +02:00 |
|
Florent Kermarrec
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54339a6d5b
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gensdrphy: fix memtype and change phase shift in comments.
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2014-05-16 16:52:24 +02:00 |
|
Sebastien Bourdeauducq
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6298624f98
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sdramphy: remove fixed parameters
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2014-05-14 16:08:40 +02:00 |
|
Sebastien Bourdeauducq
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1c08aeb21c
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Initial mor1kx (OpenRISC) support
Based on milkymist-ng-mor1kx by Stefan Kristiansson
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2014-05-14 10:24:56 +02:00 |
|
Florent Kermarrec
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774464155a
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gensdrphy: clean up and implement data mask
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2014-05-01 16:17:50 +02:00 |
|
Robert Jordens
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3ab9f234d0
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gensdrphy: use 'dm' not 'dqm' (follow s6ddrphy and majority of platforms)
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2014-04-25 10:38:57 +02:00 |
|
Florent Kermarrec
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1adceb8276
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sdramphy: move and clean up s6ddrphy, add generic SDRAM PHY
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2014-04-17 19:38:25 +02:00 |
Sebastien Bourdeauducq
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9e784fc82c
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Generate mem.h from SoC description
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2014-02-21 17:55:05 +01:00 |
|
Sebastien Bourdeauducq
|
bdb47e7977
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dvisampler: replace parity with sof
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2014-02-13 22:45:27 +01:00 |
|
Sebastien Bourdeauducq
|
42c25f44ad
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videostream: add downscaler core + test
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2014-02-10 00:12:57 +01:00 |
|
Sebastien Bourdeauducq
|
2a3803d3a1
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videostream: add single chopper
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2014-02-09 00:53:30 +01:00 |
|
Sebastien Bourdeauducq
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b6a00e86e4
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videostream: add compacter and packer
|
2014-02-08 18:39:01 +01:00 |
|
Sebastien Bourdeauducq
|
25acf17312
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Refresh testbenches and convert to new API
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2014-01-28 13:50:01 +01:00 |
|
Sebastien Bourdeauducq
|
e464935119
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downscaler: add chopper module
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2014-01-21 15:56:51 +01:00 |
|
Sebastien Bourdeauducq
|
ad974a07ef
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gensoc: support for user-defined UART and add default values for SRAM and L2 sizes
|
2014-01-06 22:12:42 +01:00 |
|
Sebastien Bourdeauducq
|
c95b9d6d76
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gensoc: use add_verilog_include_path
|
2013-12-12 23:17:16 +01:00 |
|
Sebastien Bourdeauducq
|
55a39269d2
|
gpio: add InOut
|
2013-12-06 00:06:53 +01:00 |
|
Sebastien Bourdeauducq
|
cfb9074755
|
norflash16: fix LSB
|
2013-11-30 23:06:51 +01:00 |
|
Sebastien Bourdeauducq
|
352919d17e
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norflash: add support for writes
|
2013-11-30 20:37:56 +01:00 |
|
Robert Jordens
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5953f901c8
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spiflash: add read-only variable data width spi flash
Signed-off-by: Robert Jordens <jordens@gmail.com>
|
2013-11-25 14:23:55 +01:00 |
|
Sebastien Bourdeauducq
|
96600ad9d7
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set LM32 reset address
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2013-11-25 12:09:16 +01:00 |
|
Sebastien Bourdeauducq
|
7459a849ee
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IntegratedBIOS: read only
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2013-11-25 10:25:05 +01:00 |
|
Sebastien Bourdeauducq
|
78cd7a288e
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move integrated BIOS code to gensoc
|
2013-11-25 10:22:14 +01:00 |
|
Sebastien Bourdeauducq
|
b212e0279d
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gensoc: add Papilio Pro ID
|
2013-11-24 23:50:33 +01:00 |
|
Sebastien Bourdeauducq
|
257185cc9c
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rename create_sdram_modules and add register_rom
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2013-11-24 20:16:19 +01:00 |
|
Sebastien Bourdeauducq
|
fca0b968e7
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generate linker memory map, move all generated files into the same folder
|
2013-11-24 19:50:17 +01:00 |
|
Sebastien Bourdeauducq
|
fdff1ae5f8
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make build system more generic
|
2013-11-24 13:37:32 +01:00 |
|
Sebastien Bourdeauducq
|
4a3a1d02e9
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modularize SoC integration
|
2013-11-24 10:30:02 +01:00 |
|
Sebastien Bourdeauducq
|
7496ba6360
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framebuffer: fix resynchronization after resolution change
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2013-11-21 00:33:22 +01:00 |
|
Sebastien Bourdeauducq
|
96fcb3574e
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Revert "framebuffer: reset VTG"
This reverts commit 6cb18f5ce3.
Conflicts:
misoclib/framebuffer/__init__.py
misoclib/framebuffer/format.py
|
2013-11-19 23:48:00 +01:00 |
|
Sebastien Bourdeauducq
|
2eabf97147
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dvisampler: transfer the last word in frames correctly
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2013-11-19 23:38:48 +01:00 |
|
Sebastien Bourdeauducq
|
de76e91147
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framebuffer: expose PLL DRP to CSR
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2013-11-18 20:32:33 +01:00 |
|
Sebastien Bourdeauducq
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9e883b8b02
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dvisampler: expose PLL DRP to CSR
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2013-11-18 20:32:21 +01:00 |
|
Sebastien Bourdeauducq
|
4cfcda6c8c
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framebuffer: unpack memory words in pixel clock domain for better perf
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2013-11-17 23:41:18 +01:00 |
|
Sebastien Bourdeauducq
|
c3d0985fb2
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add L2 cache size in identifier + function to flush L2
|
2013-11-16 16:27:21 +01:00 |
|
Sebastien Bourdeauducq
|
6f990a017e
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dvisampler: pack pixels in pixel clock domain to improve performance
|
2013-11-16 13:53:26 +01:00 |
|
Sebastien Bourdeauducq
|
6cb18f5ce3
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framebuffer: reset VTG
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2013-11-15 11:25:07 +01:00 |
|
Sebastien Bourdeauducq
|
34e8e8c259
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dvisampler: update address CSR at end of DMA
|
2013-11-13 18:57:10 +01:00 |
|
Sebastien Bourdeauducq
|
15499560b5
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cpuif: add memories to csr.h
|
2013-11-11 16:53:00 +01:00 |