6298624f98
sdramphy: remove fixed parameters
2014-05-14 16:08:40 +02:00
398608e997
bios: fill delay slot in boot_helper
2014-05-14 16:08:25 +02:00
94b2295a96
targets/mlabs_video: pass with_memtest as kwargs
2014-05-14 15:02:07 +02:00
13e74b8b4f
software: factorize exception_handler
2014-05-14 15:01:38 +02:00
edf567a0cd
bios: fix boot for or1k
2014-05-14 15:01:02 +02:00
1c08aeb21c
Initial mor1kx (OpenRISC) support
...
Based on milkymist-ng-mor1kx by Stefan Kristiansson
2014-05-14 10:24:56 +02:00
6f47a928b1
storage: simplify recorder...
2014-05-13 21:30:32 +02:00
c7e100f93b
sim: fix tb_trigger_csr
2014-05-13 17:45:15 +02:00
11be0a27fc
fix minimac bases addresses
2014-05-12 19:19:34 +02:00
e9db646134
mibuild: remove useless 'reduce_control_sets auto'
2014-05-12 19:11:11 +02:00
774464155a
gensdrphy: clean up and implement data mask
2014-05-01 16:17:50 +02:00
9c1d95f6a4
wishbone2lasmi: fix wordbits computation
2014-05-01 13:32:18 +02:00
87a78bc059
make.py: add missing --csr_csv argument
2014-05-01 13:31:57 +02:00
65e8b2742a
de0nano: call sdram mask dm, not dqm (follow other platforms and gensdrphy)
2014-04-25 10:40:26 +02:00
3ab9f234d0
gensdrphy: use 'dm' not 'dqm' (follow s6ddrphy and majority of platforms)
2014-04-25 10:38:57 +02:00
4c77c971f2
README: update and point to misoc-de0nano examples
2014-04-21 00:31:02 +02:00
171224329e
drivers: add genericity & prog_range_detector, prog_edge_detector methods
2014-04-21 00:17:23 +02:00
7a489b3135
refactor code
2014-04-20 23:53:33 +02:00
87a8504304
Refactor CRC tools
2014-04-19 00:01:29 +02:00
93f02a8cf4
tools: replace mkmscimg with mkmscimg.py (mkmscimg.c was platform dependent)
2014-04-18 20:22:42 +02:00
29ed3918cc
fhdl: forbid zero-length signals
2014-04-18 15:01:50 +02:00
86f852a5f1
wishbone2lasmi: support lasmim data_width < wishbone data_width
2014-04-18 15:00:53 +02:00
ea4b82e2ab
define platform.soc_ext_path when --external argument is used (to use it to include verilog files in the external target)
2014-04-18 14:56:56 +02:00
8c03cb0491
mibuild: force shell script generation to unix format (will be executed with cygwin's bash on windows)
2014-04-17 19:43:56 +02:00
d1a96bc49f
mibuild/altera_quartus: enforce use of SystemVerilog in Quartus (Verilog does not support global parameters)
2014-04-17 19:43:24 +02:00
41c35e7e0c
simple: create PowerOnRst and use it (remove vendor-dependent code)
2014-04-17 19:39:05 +02:00
1adceb8276
sdramphy: move and clean up s6ddrphy, add generic SDRAM PHY
2014-04-17 19:38:25 +02:00
2fca8d41f2
programmer: add USBBlaster and use platform.bitstream_ext in make
2014-04-17 19:32:46 +02:00
97311fc211
make: add clean action
2014-04-17 19:32:31 +02:00
362f938736
simplesoc: free LED
2014-04-14 00:23:41 +02:00
a36a208dd1
sim: use (mandatory) ncycles when starting a simulation with no active functions
2014-04-13 15:16:27 +02:00
fef08e8c70
mibuild: add bitstream_ext parameter to platforms
2014-04-11 23:28:39 +02:00
82e4980f5c
mibuild/altera_quartus: set top_level_entity
2014-04-11 23:27:04 +02:00
600ce55f91
mibuild/altera_quartus: add support for verilog include
2014-04-11 23:24:51 +02:00
4240058979
README: rewrap
2014-04-08 17:22:44 +02:00
2f6f584adb
update README
2014-04-08 17:11:27 +02:00
f76da70cda
software/libcompiler-rt: adapt to new upstream directory organization
2014-04-08 15:29:23 +02:00
0c3f8f703d
targets/simple: add dummy SDRAM + flash boot address
2014-04-08 15:25:49 +02:00
ce378f47d3
test/SyncFIFOCase: better test bench termination
2014-04-07 00:05:08 +02:00
e94f30f15d
mibuild/xilinx_ise: move overwrite option to default options
2014-04-05 12:15:15 +02:00
9ff6cc8403
mibuild/xilinx: make par and map options configurable
2014-04-05 12:15:14 +02:00
ac1363565d
genlib/fifo: add SyncFIFOClassic and SyncFIFOBuffered
2014-04-05 12:15:14 +02:00
9deddbdfbc
test/test_cordic: fix for new Simulation API
2014-03-24 15:01:44 -07:00
7649028bdc
test/support: fix default ncycles
2014-03-24 15:01:44 -07:00
0023b742e4
genlib/coding: gracefully handle flen(i) < 2
2014-03-19 18:12:27 -07:00
0836f2814a
bus/csr: new simulation api
2014-03-19 18:12:27 -07:00
b03d9f4c14
genlib/fifo: add flush, expose level in SyncFIFO
...
AsyncFIFO would need versions of flush and level in each clock domain
plus some handshaking on double flush.
Signed-off-by: Robert Jordens <jordens@gmail.com>
2014-03-15 23:10:46 -07:00
3882a07ae5
Add Python flasher
2014-02-28 09:40:49 -08:00
9e784fc82c
Generate mem.h from SoC description
2014-02-21 17:55:05 +01:00
bf6ab2b4f6
mibuild/generic_platform: fix default value for connectors
2014-02-17 17:40:15 +01:00
Sebastien Bourdeauducq
Florent Kermarrec
Robert Jordens
Sebastien Bourdeauducq