c98b9ecbcb
mibuild/platforms/papilio_pro: add expansion connectors
2014-02-16 23:54:11 +01:00
cb2c9f9f7a
mibuild: support for expansion connectors
2014-02-16 23:53:50 +01:00
fce46ac0ca
Simplify use of external targets/platforms/cores + add default platform in targets
2014-02-16 14:51:52 +01:00
f7fa9cf11e
make.py: support setting flash proxy directory
2014-02-15 14:13:25 +01:00
a23dffd2c2
bios: update banner
2014-02-15 14:02:09 +01:00
f55943ae18
new action syntax for make.py + support xc3sprog
2014-02-15 14:01:50 +01:00
e4273be517
targets/simple: use XIP from SPI flash
2014-02-14 15:48:15 +01:00
bdb47e7977
dvisampler: replace parity with sof
2014-02-13 22:45:27 +01:00
88d4962a1c
targets/mlabs_video: use outer video inputs
2014-02-13 22:07:23 +01:00
42c25f44ad
videostream: add downscaler core + test
2014-02-10 00:12:57 +01:00
2a3803d3a1
videostream: add single chopper
2014-02-09 00:53:30 +01:00
b6a00e86e4
videostream: add compacter and packer
2014-02-08 18:39:01 +01:00
d26330a9b9
Update doc with new simulation API
2014-02-07 23:08:59 +01:00
25acf17312
Refresh testbenches and convert to new API
2014-01-28 13:50:01 +01:00
2ab939e69d
fix SimActor TB terminations
2014-01-28 00:03:56 +01:00
90f0dfad63
Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator
2014-01-27 23:58:46 +01:00
63c1d7e4b7
New simulation API
2014-01-26 22:19:43 +01:00
e464935119
downscaler: add chopper module
2014-01-21 15:56:51 +01:00
8f69d9b669
bank/eventmanager: add SharedIRQ
2014-01-06 22:13:06 +01:00
ad974a07ef
gensoc: support for user-defined UART and add default values for SRAM and L2 sizes
2014-01-06 22:12:42 +01:00
be1c8551d2
migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime)
2013-12-17 18:40:49 +01:00
4e9dc297fd
platforms/rhino: add GPMC wait pin
2013-12-14 14:32:34 +01:00
a20688f777
fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems
2013-12-13 00:02:50 +01:00
3196462311
add support for Verilog include paths
2013-12-12 23:17:51 +01:00
c95b9d6d76
gensoc: use add_verilog_include_path
2013-12-12 23:17:16 +01:00
ba46cd3da1
make.py: update description
2013-12-12 23:16:59 +01:00
860f27300f
make: add decorator option
2013-12-12 17:37:46 +01:00
adda930c68
fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs
2013-12-12 17:37:31 +01:00
adffec35f6
utils/misc: add gcd_multiple function to compute GCD or any number of integers
2013-12-12 17:36:50 +01:00
c13fe1bc63
specials/Memory: allow for more flexibility in memory port signals
2013-12-12 17:36:17 +01:00
9aa474c6f0
gitmodules: use https and m-labs
2013-12-12 15:56:06 +01:00
135a4fea25
fhdl/verilog: fix representation of negative integers
...
Give the explicit two's complement representation for the given bit width.
This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
2013-12-11 22:26:10 +01:00
d6cb981c7a
migen/test/test_signed: add a (currently failing) signed comparison testcase
2013-12-10 23:33:53 +01:00
487df5b174
migen/fhdl/bitcontainer: fix signed arrays (map is an iterator)
2013-12-10 23:32:12 +01:00
fe0263bb9a
mibuild/xilinx_ise: use ngdbuild_opt also for xst case
2013-12-06 12:15:22 +01:00
0aa6329edb
mibuild/xilinx_ise: add support for custom tools and options
2013-12-06 09:16:07 +01:00
58e9792132
update submodule
2013-12-06 00:07:05 +01:00
55a39269d2
gpio: add InOut
2013-12-06 00:06:53 +01:00
65f3c1ddff
targets/mlabs_video: use new Cat syntax
2013-12-05 23:55:14 +01:00
e09e85ec8e
usrp_b100 platform
2013-12-03 22:51:52 +01:00
5447eb51ba
add zedboard platform
2013-12-03 22:51:52 +01:00
bfdc14fbc3
add initial ztex_115d platform
2013-12-03 22:51:52 +01:00
8d093a4a08
lx9 fixups
2013-12-03 22:51:52 +01:00
8d3d61ba98
fhdl.size: rename to bitcontainer
2013-12-03 22:51:52 +01:00
86ba9c8bbc
migen.fhdl.size: verify fslice for negative values
2013-12-03 21:39:37 +01:00
440b7d5170
make/_misoc_import: force external path search
2013-12-03 21:36:58 +01:00
c71eb5778f
migen.fhdl.structure: have Cat() flat_iteration-ize its arguments
2013-12-03 21:36:33 +01:00
1bf133755e
migen.fhdl.tools: move flat_iteration to migen.util.misc as tools imports other things
2013-12-03 21:36:33 +01:00
fe67210d77
migen.fhdl.size: add fiter(), fslice(), and freversed()
...
do not overload __len__, __iter__, __reversed__ as not all valid
expressions (ints and bools) have them. furthermore len([]) is and
should be different from flen([]) (the later raises an error). keep
__getitem__ as an exception that proves the rule ;)
2013-12-03 21:36:33 +01:00
ae6b78faeb
genlib/divider: fix diff computation
2013-12-02 17:56:03 +01:00
Sebastien Bourdeauducq
Sebastien Bourdeauducq
Robert Jordens