797411c1a9
generic_platform: do not create clock domains during Verilog conversion
2013-03-18 18:44:58 +01:00
af4eb02551
examples/basic/arrays: demonstrate lowering of Array in Instance expression
2013-03-18 18:37:23 +01:00
7a06e9457c
Lowering of Special expressions + support ClockSignal/ResetSignal
2013-03-18 18:36:50 +01:00
48aae9bee5
Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
2013-03-18 17:44:01 +01:00
dc55289323
fhdl/tools/_ArrayLowerer: complete support for arrays as targets
2013-03-18 14:38:01 +01:00
e95d2f4779
fhdl/tools/value_bits_sign: support not
2013-03-18 09:52:43 +01:00
0c0140a8fb
m1crg: set CLKIN_PERIOD for vga_clock_gen
2013-03-17 20:16:58 +01:00
74cc045ee1
dvisampler/datacapture: connect IODELAY IOCLK0
2013-03-17 17:42:22 +01:00
621526fb7d
dvisampler/datacapture: fix tap counter reg
2013-03-17 17:36:49 +01:00
3a0cf278fd
dvisampler: fixes
2013-03-17 15:41:50 +01:00
b6fe3ace05
fhdl/structure: style fix
2013-03-17 15:33:38 +01:00
2a4cc3875c
Merge pull request #6 from larsclausen/master
...
Minor improvements
2013-03-17 07:33:14 -07:00
9f02ced39e
dvisampler: add clocking and phase detector
2013-03-17 14:43:10 +01:00
4bf3190244
MultiReg: remove idomain
2013-03-15 19:54:25 +01:00
0168f83523
MultiReg: remove idomain
2013-03-15 19:51:29 +01:00
2f522bdd9f
genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains
2013-03-15 19:50:24 +01:00
e2d156ef64
genlib/cdc/MultiReg: remove idomain
2013-03-15 19:49:24 +01:00
7b49fd9386
fhdl/specials: fix rename_clock_domain declarations
2013-03-15 19:47:01 +01:00
51bec340ab
sim: remove PureSimulable (superseded by Module)
2013-03-15 19:41:30 +01:00
b2173bba9f
Use new ClockDomain API
2013-03-15 19:17:05 +01:00
dd0f3311cd
structure: remove Fragment.call_sim
2013-03-15 19:15:48 +01:00
9b9bd77d00
sim: compatibility with new ClockDomain API
2013-03-15 19:15:28 +01:00
6feb6e60b0
New clock_domain API
2013-03-15 18:46:11 +01:00
208e039bbb
Local clock domain example
2013-03-15 18:18:32 +01:00
bd8bbd9305
Make ClockDomains part of fragments
2013-03-15 18:17:33 +01:00
001beadb97
altera_quartus, de0nano: add copyright notices
2013-03-15 12:37:25 +01:00
f9e07b92a4
Added platform file for DE0 Nano (by Florent Kermarrec)
2013-03-15 11:41:38 +01:00
86d6f1d011
Added support for Altera Quartus (by Florent Kermarrec)
2013-03-15 11:32:12 +01:00
71c8172836
xilinx_ise/CRG_SE: reset inversion support
2013-03-15 11:31:36 +01:00
37d8029848
CRG: support reset inversion
2013-03-15 10:49:18 +01:00
24910173b7
CRG: use new Module API
2013-03-15 10:48:43 +01:00
5adab17efa
flow/actor/filter_endpoints: deterministic order
2013-03-14 12:20:18 +01:00
fc883198ae
bank/csrgen/BankArray: create banks in sorted order
2013-03-13 23:07:44 +01:00
2ae504fb9b
software/bios: default length 4 for mr command
2013-03-13 19:59:39 +01:00
eaef3464e9
Instantiate DVI sampler core for both ports
2013-03-13 19:56:56 +01:00
e99bafe52b
dvisampler: add core, EDID support
2013-03-13 19:56:26 +01:00
52d13959f2
bank/description: modify reg/mem in-place
2013-03-13 19:46:34 +01:00
dea4674922
Allow SimActors to produce/consume a constant stream of tokens
...
Currently a SimActor requires one clock period to recover from consuming or
producing a token. ack/stb are deasserted in the cycle where the token is
consumed/produced and only re-asserted in the next cycle. This patch updates the
code to keep the control signals asserted if the actor is able to produce or
consume a token in the next cycle.
The patch also sets 'initialize' attribute on the simulation method, this will
make sure that the control and data signals will be ready right on the first
clock cycle.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 23:10:51 +01:00
72579a6129
Add support for negative slice indices
...
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].
Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
reg.eq(Cat(Replicate(0, n), reg[-n:])
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
c99cc9343f
examples/pytholite: use new APIs
2013-03-12 16:59:24 +01:00
69dbf84e54
sim/generic: support implicit get_fragment
2013-03-12 16:54:01 +01:00
d92ca43cd0
vpi: make it work by default on Arch
2013-03-12 16:51:58 +01:00
907bfa87f4
examples/basic: use new APIs
2013-03-12 16:45:28 +01:00
ecfe1646ec
fhdl/verilog: implicit get_fragment
2013-03-12 16:16:06 +01:00
c06a821452
generic_platform: implicit get_fragment
2013-03-12 16:14:13 +01:00
1e7783a41e
build.py: use implicit get_fragment
2013-03-12 16:13:20 +01:00
4ada2ead05
fhdl/specials/Memory: automatic name#
2013-03-12 15:58:39 +01:00
a23df42a7a
Use automatic register naming
2013-03-12 15:47:54 +01:00
04df076fba
bank: automatic register naming
2013-03-12 15:45:24 +01:00
7e2581bf17
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
2013-03-12 13:48:09 +01:00
Sebastien Bourdeauducq
Lars-Peter Clausen