a6d076f810
litex_setup: Reorganize code with functions.
2021-10-26 11:36:38 +02:00
5c0e951dc3
litex_setup: Cleanup/Simplify.
2021-10-26 10:49:34 +02:00
71a91eac15
test: Rename test_boot.py to test_cpu.py.
2021-10-26 08:35:16 +02:00
9b4c7e8288
README/litex_setup: Remove reference to LiteVideo to encourage use of LiteX's VideoTerminal/Out core.
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LiteVideo is not longer maintained, does not have CI and is messy (code is ~10 years old where we were
still experimenting the innovative approach with Migen). The core is kept since can be useful as reference
for Video Input and for projects using it but it is not recommended for new designs.
2021-10-26 08:21:00 +02:00
07bd8ed65b
Merge pull request #1082 from enjoy-digital/mithro-patch-1
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Fix a misspelling in README
2021-10-26 07:51:35 +02:00
a6d8679f78
Fix a misspelling
2021-10-25 17:20:48 -07:00
8c62bb8d2e
fhdl/memory_efinix: Add efx to transformed memories to avoid conflicts.
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Fix the crash with the LiteX identifier.
2021-10-25 19:32:18 +02:00
7914923d2d
soc/build: Avoid no_we mode on RAMs and move specialization of Efinix memories to fhdl.
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Specialization still only support 32-bit RAMs and will still need to be refactored.
2021-10-25 19:08:09 +02:00
a3678c1298
build/efinix/ifacewriter: Remove add_ddr_xml (too early to support it).
2021-10-25 18:17:07 +02:00
0ed3803291
cores/clock/efinix_trion: Switch to excluded_ios and simplify create_clkout.
2021-10-25 18:14:45 +02:00
fff5895130
build/efinix: Avoid deleting IOs from platform (too complicated), just use an excluded IOs list.
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Also remove generic_platform's delete that was only used for here.
2021-10-25 18:13:56 +02:00
5dc377eda1
clock/efinix_trion: Cleanup PLL block, fix reset polarity and always enable it.
2021-10-25 17:49:39 +02:00
36b26006a4
fhdl/verilog: Only collect IOs when ios set is empty.
2021-10-25 17:17:50 +02:00
7662ec5531
clock/efinix_trion: Replace ' with ".
2021-10-25 17:11:10 +02:00
cfc0b1d337
clock/efinix_trion: Remove count (this will have to be correctly implemented).
2021-10-25 17:09:47 +02:00
8dc727b514
build/efinix/common: Cleanup EfinixTristateImpl.
2021-10-25 15:00:43 +02:00
ce1660da4d
generic_platform/fhdl/verilog: Move IOs collection to fhdl/verilog.
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IOs can be genererated while lowering specials on Efinix FPGAs.
2021-10-25 14:40:21 +02:00
0784fd0396
build/efinix/__init__.py: Remove EfinixDDR import.
2021-10-25 12:43:28 +02:00
c04753bd3a
build/efinix: Remove ddr/rgmii/video cores support (will have to be integrated properly in LiteDRAM/LiteEth/LiteX and integrated in LiteX-Boards).
2021-10-25 12:32:30 +02:00
cab1742cf0
build/efinix: Remove useless () on classes.
2021-10-25 12:23:36 +02:00
e6f7dbe69b
build/efinix/dbparser: Fix syntax error.
2021-10-25 11:36:23 +02:00
a083c34e47
Merge pull request #1078 from trabucayre/efinix_pllv1
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efinix: pll v1 (T4/T8) support
2021-10-25 11:26:46 +02:00
47b3c9bc08
soc/interconnect/packet: Remove last_be support in LiteX, specialized Packetizer/Depacketizer have been moved to LiteEth to simplify development and avoid eventual regresion on others cores.
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As seen during the last LiteEth developments, last_be data qualifier is not easy to handle correctly and should be replaced by a simpler data qualifier (similar to AXI's tkeep/tstrb). It will
be easier to do so by having a local copy of Packetizer/Depacketizer directly in LiteEth (still with last_be support) and work on the simpler data qualifier in LiteX (and test it on LitePCIe).
2021-10-25 11:17:36 +02:00
96101521be
Merge pull request #1079 from lschuermann/dev/xgmii-rx-fcs
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litex_sim/xgmii_ethernet: fix RX frame check sequence generation
2021-10-25 10:30:05 +02:00
f2a622975a
litex_sim/xgmii_ethernet: fix RX frame check sequence generation
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The rewritten XGMII Ethernet module generates proper frame check
sequences (FCS) on Ethernet frames received by the simulation, such
that the unmodified MAC pipeline including CRC checking can be
used. However, the byte order of the generated frame check sequence
has been inverted. This becomes apparent when one specifies that the
CRC should be calculated in the LiteX BIOS.
This fixes the byte order to be correct. The similar GMII Ethernet
module did not contain this mistake.
Fixes: 7b533a032d
2021-10-25 08:57:36 +02:00
3c209c6c1f
efinix: pll v1 (T4/T8) support
2021-10-24 17:39:57 +02:00
2886fe1701
Add bios test mode for CI ( #1076 )
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* Add bios test mode for CI
This enables to test the booting of each CPU configurations with the bios in Verilator simulation.
2021-10-24 12:08:58 +02:00
8e448592f0
interconnect/packet: Revert old last/ready logic handling (new one breaks test_packet) and comment out test_packet2 tests (does not seems to be working with previous last/ready handling).
2021-10-23 18:21:47 +02:00
59fd2d31c7
test/test_packet2: Fix imports.
2021-10-23 17:54:00 +02:00
f3f9737697
interconnect/packet: Add FIXME notes.
2021-10-23 17:43:55 +02:00
32bb2554bc
test: Rename new test_packet/stream to test_packet2/stream2 and revert old tests.
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Old and new tests are complementary and would need to be merged.
2021-10-23 17:40:41 +02:00
434b3a3654
Merge pull request #1008 from lschuermann/dev/packetizer-last_be-fix
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{Dep,P}acketizer: properly handle last_be wraparound
2021-10-23 17:33:29 +02:00
af66f8d2ec
litex_setup: Switch to pythondata-cpu-ibex.
2021-10-23 17:26:25 +02:00
adc3aecc56
Merge pull request #1074 from navan93/use-ibex-main-repo
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Use ibex main repo
2021-10-23 17:24:04 +02:00
68b67af1bd
build/efinix/common: Add initial Tristate/SDRTristate support.
2021-10-22 20:02:17 +02:00
89b66be323
build/efinix/efinity: Fix Slice case on get_pin_location/get_pin_name.
2021-10-22 20:01:31 +02:00
62c7978cfd
fhdl/verilog: Add optional platform parameter and set platform to specials.
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Being able to access the platform when lowering specials is required for Efinity.
2021-10-22 20:00:27 +02:00
2a775e1493
efinix/efinity: Remove spi_low_power_mode (Prevents BIOS XiP).
2021-10-22 10:41:42 +02:00
f7a256bc5b
tools/litex_client: Add --length parameter for MMAP read accesses.
2021-10-22 09:07:19 +02:00
14c39c0f2b
Merge pull request #1075 from cr1901/sb_io-pin_input
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Set LatticeiCE40SDROutputImpl to `PIN_INPUT` mode.
2021-10-22 09:05:26 +02:00
140e4586ab
Use PIN_INPUT mode in LatticeiCE40SDROutputImpl because i_INPUT_CLK is not connected.
2021-10-21 12:11:52 -04:00
6f8fbfb619
soc/add_cpu: Avoid checking variant with CPUNone.
2021-10-21 11:44:45 +02:00
d16d4917d6
build/openfpgaloader: Allow reuse of programmer for consecutive commands and fix --offset.
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- Avoid appending to self.cmd on each load_bitstream/flash call to allow reused of programmer object.
- Convert address to str.
2021-10-21 11:25:32 +02:00
a7a746473d
Fix missing include in ibex
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Change Ibex to use pythondata-cpu-ibex package and also fix the error of missing include by adding the dependency files first to the list of source files. As mentioned in lowRISC/ibex#1461 .
2021-10-20 18:26:02 +05:30
cf2e073b14
Add changes to use Ibex from pythondata-cpu-ibex
2021-10-20 07:28:13 +05:30
8fa4de5ede
cores/video: Interpret CSI Move Up as Clear XY.
2021-10-19 17:24:41 +02:00
8945d74aa3
litex_setup: Bump pythondata-misc-opentitan (and update Get SHA1 command).
2021-10-19 15:47:24 +02:00
b9545c2276
cpu/ibex: Add local patch to fix missing import.
2021-10-19 15:43:27 +02:00
f4bd729d28
Merge pull request #1070 from navan93/ibex-irq-support
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Fix the support for Ibex.
2021-10-19 15:43:12 +02:00
78237fffd9
cores/cpu: Avoid complex port types on microwatt_wrapper.
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microwatt_wrapper.vhdl was introduced for this since some toolchains don't
support complex VHDL ports types on verilog instances (ex previous version
of Vivado).
2021-10-19 15:04:12 +02:00
Florent Kermarrec
Tim Ansell
Leon Schuermann
Gwenhael Goavec-Merou
Navaneeth Bhardwaj
William D. Jones