ae1d43b965
software/libc/Makefile: Use proper CFLAGS to avoid picolibc warnings and cleanup a bit Makefile.
2021-09-27 16:14:55 +02:00
c0b54f0105
Merge pull request #976 from antmicro/libbase-replacement
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Replace libbase with picolibc
2021-09-27 16:05:24 +02:00
944732aa19
soc/add_sdram: Also remove ResetInserter on axi.AXI2Wishbone.
2021-09-27 15:46:19 +02:00
06ff638f7a
efinix: rgmii: fix, it's in a working state
2021-09-27 10:11:58 +02:00
1ea0797c82
efinix: ifacewriter: fix DRIVE_STRENGTH and REFCLK_FREQ
2021-09-27 10:11:00 +02:00
ce0551b44a
cpu/rocket/core: Remove ResetInserter on adapters.
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Previously, the SoCController was only reseting the CPU, which required adding
these ResetInserters. Now that the SoCController resets both CPU and peripherals
these ResetInserters are redundant and no longer useful.
2021-09-27 09:05:46 +02:00
179a8018b3
efinix: RGMII phy should be operational (no tested)
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PLL infrastructure should be complete now.
We can also use DDIO input and outputs.
However, there is problem (bug) during P&R:
ERROR(1): [Line 52] Block auto_eth_tx_delayed_clk is
an output pad but sub-block 1 is not an output pad location.
Inderface Designer validation doesn't report any problem.
I have a test project with the same configuration (I compared
the reports for blocks configuration) and it works.
2021-09-23 17:21:17 +02:00
c43132f81f
Merge pull request #1040 from gsomlo/gls-rocket-smp
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Rocket SMP support
2021-09-23 10:56:06 +02:00
07e47d9357
cpu/rocket: add quad-core (smp) variants
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- 4-core "full" (fpu-enabled) variants with double, quad mem. bus width
- 4-core "linux" (fpu-less) variant with single (64-bit) mem. bus width
2021-09-22 16:59:04 -04:00
901b19828c
cpu/rocket: include core count as per-variant parameter
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Repurpose (and rename to `CPU_SIZE_PARAMS`) the current
`AXI_DATA_WIDTHS` array. In addition to axi widths for
mem and mmio ports, also include each variant's number
of cores, to facilitate dynamically generated per-core
signals.
2021-09-22 16:58:11 -04:00
e6aaa40d2d
cpu/rocket: bios support for SMP
2021-09-22 13:51:18 -04:00
2bc8124114
cpu/rocket: crt0, boot-helper: use temp. registers (cosmetic)
2021-09-22 13:51:18 -04:00
1d302c56da
Merge pull request #1041 from gsomlo/gls-vex-smp-fix
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cpu/vexriscv_smp/crt0.S: only boot core should run data_init
2021-09-22 19:35:47 +02:00
60c6077c32
remote/comm_udp: Add padding bytes to Etherbone probe.
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Now required with LiteEth dropping exceeding payload.
2021-09-22 16:52:08 +02:00
23b2ac2013
cpu/vexriscv_smp/crt0.S: only boot core should run data_init
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Also, no need for non-boot cores to `call smp_slave`, it's the
immediately following instruction for them already.
2021-09-22 09:55:20 -04:00
109dbd1d62
efinity: small fixes
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- do not include *.vh files in project,
- add self.options to class EfinityToolchain
- remove unconditional call to self.ifacewriter.add_ddr_xml
2021-09-22 09:53:27 +02:00
b24475b07d
Add an hacked no we memory for Efinix
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Efinity synthesizer cannot infer RAM blocks with write enable.
In order to workaround this (at least for the Litex SoC intergrated
RAM/ROM) a dirty modified Memory class has been created.
This class needs to be rewrite !
2021-09-22 09:47:51 +02:00
027f7aa645
tools/litex_json2dts_linux: Fix typo.
2021-09-21 14:32:20 +02:00
bd71dc663f
efinix: more DDR work, still WIP
2021-09-21 14:23:36 +02:00
b765bdf34e
efinix: pll: allow output name to be changed
2021-09-21 14:23:00 +02:00
7a5f5a3682
efinix: remove redundant param in _build_xml
2021-09-21 14:22:17 +02:00
84f1afd6d4
tools/litex_json2dts_linux: Remove mem=/, init= and swiotlb= bootargs.
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Were not useful as pointed by @shenki and @stffrdhrn.
2021-09-21 13:37:25 +02:00
b1b1e92ad0
Merge pull request #1032 from stffrdhrn/json2dts-sdcard
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Json2dts sdcard booting
2021-09-21 13:13:07 +02:00
24a920f2d1
efinix: add preliminary DDR support (WIP)
2021-09-21 10:58:54 +02:00
9f75c73d6b
build/xilinx/common: Fix Ultrascale SDROutput/Input.
2021-09-21 10:30:36 +02:00
233f0fc5f4
Merge pull request #1039 from tcal-x/rm-response-ok
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Remove rsp_payload_response_ok from Vex/CFU hookup code.
2021-09-21 09:43:15 +02:00
08779202f4
build/DDRTristate: Fix inconsistencies with SDRTristate (o/i swap).
2021-09-21 08:18:06 +02:00
1be449d72b
Remove rsp_payload_response_ok from Vex/CFU hookup code.
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The port has already been removed from VexRiscv (issue #1036 ).
Signed-off-by: Tim Callahan <tcal@google.com>
2021-09-20 15:02:51 -07:00
1e24fd87d1
cores/gpio: Simplify #1035 .
2021-09-20 17:34:46 +02:00
6251474b39
Merge pull request #1035 from lschuermann/dev/litex-sim-gpio
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litex_sim: optionally add GPIOTristate core
2021-09-20 17:21:29 +02:00
0daa86a8bb
Merge pull request #1038 from antmicro/crosslinknx-ddr-tristate
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build/lattice: add DDRTristate for Crosslink-NX
2021-09-20 14:14:40 +02:00
49d8000d49
gowin/common: Add Differential Input/Output support.
2021-09-20 14:14:06 +02:00
b9e99f576c
efinix: use proper xml to create project file
2021-09-20 13:35:45 +02:00
9c373242af
gowin: Add HyperRAM integration hack to match Gowin EDA expected pattern.
2021-09-20 11:47:32 +02:00
6c0a758468
Added syn_useioff attribute support for Oxide toolchain and for the DDRTristate in Crosslink NX
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-20 11:02:01 +02:00
efebefecea
efinix: add PLL reset and locked pins
2021-09-20 10:42:27 +02:00
a026dd8946
efinix: add AsyncResetSynchronizer
2021-09-20 10:41:59 +02:00
08be77caaf
efinix: ifacewriter, enable design generation
2021-09-20 10:41:00 +02:00
5519d908e8
cores/video: Rename VideoECP5HDMIPHY to VideoHDMIPHY since in fact generic and can be used on other FPGAs (ex Tang Nano 4k).
2021-09-20 09:29:05 +02:00
106b1f29a7
efinix: fix programmer load_bitstream
2021-09-20 08:42:27 +02:00
4fe085cc1c
cores/clock: Add initial GW1NSR's PLL support.
2021-09-20 08:39:25 +02:00
76c782c546
inetgration/builder: Check for full software re-build only when a CPU is used.
2021-09-20 08:31:22 +02:00
9b6ae2ff03
efinix: support PLL, add dbparser and ifacewriter
2021-09-20 07:56:53 +02:00
0278d3eee8
generic_platform: add a method to delete a constraint
2021-09-20 07:51:26 +02:00
46cd9c5a5c
tools: Minor #1030 cleanups.
2021-09-17 14:37:48 +02:00
8ccb1a91c9
build/openfpgaloader/flash: Add external parameter to allow flashing external SPI Flash when available.
2021-09-17 14:37:14 +02:00
24f0432253
Merge pull request #1030 from teknoman117/fix-lxserver-pcie-crossover
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Fixes to allow crossover uart over PCIe with lxterm and litex_server
2021-09-17 14:28:25 +02:00
a7c9e4ed42
Merge pull request #1033 from caverar/patch-1
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Linker fix for initialized global variables
2021-09-17 14:23:44 +02:00
000aabf85b
Initial Efinix Trion support
2021-09-17 09:29:53 +02:00
7f8e2e39f3
cores/video/VideoECP5HDMIPHY: Allow pn_swap on data lanes.
2021-09-16 18:56:05 +02:00
Florent Kermarrec
Franck Jullien
Gabriel Somlo
Andwer E Wilson
Tim Callahan
Maciej Kurc