192849f0b6
Merge pull request #475 from gregdavill/read_verilog_defer
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build/trellis: add verilog_read -defer option to yosys script
2020-04-27 13:13:37 +02:00
642c4b3036
build/trellis: add verilog_read -defer option to yosys script
2020-04-27 20:10:25 +09:30
71778ad226
serv: update copyrights (Greg Davill found the typos/issues).
2020-04-27 10:27:44 +02:00
1f9db583fd
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
2020-04-26 21:05:47 +02:00
2efd939d06
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
2020-04-26 16:26:57 +02:00
96e7e6e89a
bios/sdram: reduce number of scan loops during cdly scan to speed it up.
2020-04-25 12:51:33 +02:00
43e1a5d67d
targets/kcu105: use cmd_latency=1.
2020-04-25 12:12:27 +02:00
85a059bf77
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
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We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
2020-04-25 12:11:10 +02:00
038e1bc048
targets/kc705: manual DDRPHY_CMD_DELAY no longer needed.
2020-04-25 11:03:04 +02:00
aaed4b9475
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
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Working on KC705 that previously required manual adjustment.
2020-04-25 11:00:21 +02:00
33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration
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bios/sdram: add automatic cdly calibration during write leveling
2020-04-25 09:59:08 +02:00
4608bd1864
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings
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litex_sim: add option to create SDRAM module from SPD data
2020-04-25 08:27:00 +02:00
a344e20b5e
spi_flash: fix building without bitbang
2020-04-24 17:45:17 +02:00
ab92e81e31
bios/sdram: add automatic cdly calibration during write leveling
2020-04-24 14:00:42 +02:00
22c3923644
initial SERV integration.
2020-04-23 08:18:41 +02:00
0b3c4b50fa
soc/cores/spi: add optional aligned mode.
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In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
6bb22dfe6b
cores/spi: simplify.
2020-04-22 12:20:23 +02:00
fc434af949
build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt).
2020-04-22 12:01:23 +02:00
1457c32052
xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale.
2020-04-22 10:42:06 +02:00
69462e6669
build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
2020-04-22 10:33:22 +02:00
65e6ddc6cd
lattice/common: add LatticeECP5DDRInput.
2020-04-22 10:13:28 +02:00
2031f28057
lattice/common: cleanup instances, simplify tritates.
2020-04-22 09:07:38 +02:00
2d25bcb09c
lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput.
2020-04-22 09:07:33 +02:00
56e1528455
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
2020-04-18 11:38:24 +02:00
08e4dc02ec
tools/remote/etherbone: update import.
2020-04-17 21:30:33 +02:00
b0f8ee9876
litex_sim: add option to create SDRAM module from SPD data
2020-04-17 14:52:53 +02:00
19f983c420
targets: manual define of the SDRAM PHY no longer needed.
2020-04-16 11:26:59 +02:00
c0f3710d66
bios/sdram: update/simplify with new exported LiteDRAM parameters.
2020-04-16 10:42:01 +02:00
3915ed9760
litex_sim: add phytype to PhySettings.
2020-04-16 10:22:43 +02:00
c0c5ae558a
build/generic_programmer: move requests import to do it only when needed.
2020-04-16 08:44:36 +02:00
c9ab593989
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
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Bitslip software control is now used on ECP5 to move dqs_read.
2020-04-15 19:30:28 +02:00
2d01882653
setup.py/install_requires: add requests.
2020-04-15 09:27:26 +02:00
5e149ceda2
build/generic_programmer: add automatic search/download of flash_proxy in repositories if not available locally.
2020-04-15 08:59:03 +02:00
a298a9e568
Merge pull request #467 from antmicro/region_type_fix
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soc_core: Fix region type generation
2020-04-15 07:56:48 +02:00
77a05b78e8
soc_core: Fix region type generation
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Include information about being a linker region.
2020-04-14 21:45:32 +02:00
d44fe18bd9
stream/AsyncFIFO: add default depth (useful when used for CDC).
2020-04-14 17:35:19 +02:00
ded10c89dc
build/sim/core/Makefile: add -p to mkdir modules.
2020-04-14 12:38:02 +02:00
c323e94c83
Merge pull request #464 from mithro/litex-sim-fixes
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Improve the litex_sim Makefiles
2020-04-14 12:16:21 +02:00
a8bf02167a
litex_setup: raise exception on update if repository has been been initialized.
2020-04-12 19:46:56 +02:00
97d0c525ee
Remove trailing whitespace.
2020-04-12 10:29:13 -07:00
4fe31f0760
cores: add External Memory Interface (EMIF) Wishbone bridge.
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Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
44746870a7
Merge pull request #462 from ironsteel/trellis-12k
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Add support for ecp5 12k device in trellis.py
2020-04-12 15:49:49 +02:00
c57e438df6
boards/targets/ulx3s.py: Update --device option help message
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Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 12:01:31 +03:00
f4b345ecd7
build/lattice/trellis.py: Add 12k device
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nextpnr adds the --12k option which is the same like
the --25k but with the correct idcode for the 12k devices
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 11:46:44 +03:00
1f35669508
litex_sim: Find tapcfg from pythondata module.
2020-04-11 18:38:15 -07:00
3aee8a5227
Remove directories from submodules from MANIFEST.in file.
2020-04-11 18:37:06 -07:00
ebcb2a4406
Rename litex-data-XXX-YYY to pythondata-XXX-YYY
2020-04-11 18:37:06 -07:00
a39a4ec2ed
Only allow fast-forward pulls.
2020-04-11 18:37:06 -07:00
e618d41ffb
Fixing mor1kx data finding.
2020-04-11 18:37:06 -07:00
2e3b7f20c7
Fix typo in error message.
2020-04-11 18:37:06 -07:00
enjoy-digital
Greg Davill
Jakub Cebulski
Jędrzej Boczar
Mateusz Holenko
Tim 'mithro' Ansell
Rangel Ivanov