1ce48a973b
clock/lattice_ecp5: Fix and rework 4-output solver implementation.
...
The implementation was causing regressions on actual designs, rework done:
- Only keep a common iteration loop as before.
- Add iteration on CLKO dividers (to fall in the VCO range).
- Do the iterations as before, if while doing it we find a clock suitable for feedback: just use it.
- If no feedback clock has been found: create it (if at least one free output available, if not raise an error).
2021-07-26 14:00:00 +02:00
8954041a93
clock/lattice_ecp5/ECP5PLL: Only consider non-dpa clocks as feedback
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Dynamically adjusting the phase of a feedback will cause it to unlock.
The phase adjust ports are shared by all the outputs, so there is no
technical way to prevent this. Allow the user to indicate that they
will not adjust a clock when requesting an output by setting
uses_dpa=False, and only consider those that the user has promised not
to use.
2021-07-08 08:14:14 -05:00
f6b2135cc9
test/test_timer: Update.
2021-05-27 19:37:51 +02:00
675349055b
inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2.
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Allow supporting all cases.
2021-03-18 13:47:10 +01:00
98b75d8671
Add initial core test for Timer
2021-01-21 21:37:41 -06:00
f31f9a20f0
boards: remove and switch to litex_boards.
...
Keeping board definition files directly in LiteX is no longer useful since we are already relying on board
definitions files from LiteX-Boards (https://github.com/litex-hub/litex-boards ) in various benches/projects
and having definitions files directly in LiteX creates confusion/additional work.
For projects using board definition files from LiteX, the litex.boards import can just be replaced with litex_boards:
from litex.boards.platforms import kc705
from litex_boards.platforms import kc705
2021-01-04 14:09:35 +01:00
6771ed0796
ci: migrate from Travis CI to Github Actions.
2020-11-24 15:55:49 +01:00
cecb36d608
test/test_clock: update with new supported devices.
2020-11-09 10:37:20 +01:00
e91ec2ed83
soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams).
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With improvements to handle backpressure on non-continous streams.
2020-10-21 09:29:21 +02:00
305092c7b8
test/test_icap: update.
2020-10-07 12:36:08 +02:00
f7b6dd05ae
cores/clock: add initial Xilinx Ultrascale Plus PLL/MMCM/IDELAYCTRL support.
2020-09-03 18:58:10 +02:00
77ae243310
test: add SPDX License identifier to header and specify file is part of LiteX.
2020-08-23 15:40:21 +02:00
a5d0a340c3
test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces.
2020-08-04 09:39:23 +02:00
e78d950a31
soc/interconnect/axi: add AXILite -> AXI converter
2020-07-30 13:50:34 +02:00
879e6ffe73
soc/interconnect/axi: add basic AXI Lite up-converter
2020-07-24 13:47:18 +02:00
32160e615f
soc/interconnect/axi: separate AXI Lite converter channels
2020-07-24 09:25:57 +02:00
a9d8b81385
test/axi: move all AXI Lite tests to separate file
2020-07-22 17:16:33 +02:00
8ae501c391
test/axi: add crossbar stress tests
2020-07-22 17:16:33 +02:00
32d9e212c5
soc/interconnect/axi: improve Timeout module and test it with shared interconnect
2020-07-22 17:16:33 +02:00
2cab7fbf0f
test/axi: add shared AXI Lite interconnect tests
2020-07-22 17:16:33 +02:00
3a08b21d44
soc/interconnect/axi: implement AXI Lite decoder
2020-07-22 17:16:33 +02:00
214cfdcaeb
soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to
2020-07-22 17:16:33 +02:00
baf23c9c9b
test/test_axi: add AXI Lite interconnect arbiter tests
2020-07-22 17:16:29 +02:00
f47ccdae99
soc/interconnect/axi: point-to-point interconnect and timeout module with tests
2020-07-22 17:16:12 +02:00
47ce15b431
interconnect/wishbone: add minimal UpConverter.
2020-07-21 19:35:14 +02:00
100aa5a4ca
soc/cores/spi/SPIMaster: rewrite/simplify.
...
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
2020-07-20 10:44:18 +02:00
93bcc94b53
soc/interconnect/axi: implement AXILite down-converter
2020-07-16 17:02:49 +02:00
78a631f392
test/axi: add AXILite2CSR and AXILiteSRAM tests
2020-07-15 12:40:39 +02:00
5d202ddb97
test: update.
2020-06-02 13:51:48 +02:00
80ec5eca76
boards/arty: remove specific arty_symbiflow platform and adapt target to use standard platform.
2020-06-02 12:18:12 +02:00
7434376c07
test/test_targets: add arty_symbiflow
...
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
2020-06-01 21:41:56 +02:00
3d06dc028c
test/test_targets: update build_test.
2020-05-22 08:42:02 +02:00
ce49990084
Extend I2S capabilities
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This commit:
* adds the support for I2S standard mode,
* extends I2S left justified mode,
* allows to configure sample size for tx/rx in 1-32 bits range,
* implements I2S master mode,
* allows to concatenate channels or used the padded mode.
This required to rework the FSM.
2020-05-20 14:31:51 +02:00
6f8f0d2346
litex_setup: add litehyperbus and remove hyperbus core/test.
2020-05-19 15:49:25 +02:00
9f941138d2
test/test_targets: workaround to fix travis.
2020-05-13 11:04:40 +02:00
98d1b45157
platforms/targets: fix CI.
2020-05-05 15:55:09 +02:00
0b3c4b50fa
soc/cores/spi: add optional aligned mode.
...
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
4fe31f0760
cores: add External Memory Interface (EMIF) Wishbone bridge.
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Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
383fcd36d6
soc/cores/clock: add CycloneVPLL.
2020-04-07 17:24:12 +02:00
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
c154d8d2fc
test/test_targets: remove versa_ecp3.
2020-03-25 08:47:43 +01:00
f03d862c06
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-20 23:46:15 +01:00
eb9f54b2bc
test: add initial (minimal) test for clock abstraction modules.
...
Also fix divclk_divide_range on S6DCM.
2020-03-13 12:38:23 +01:00
54fb3a61cd
test/test_targets: use uart-name=stub.
2020-02-29 11:07:10 +01:00
1d70ef6958
soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now)
2020-02-06 17:58:01 +01:00
f58e8188b7
soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores.
2020-02-06 17:00:04 +01:00
f3f9808d1f
interconnect/stream: add PipeValid and PipeWait to cut timing paths.
2020-01-29 18:27:29 +01:00
7b92a17c6e
test/test_targets: limit max_sdram_size to 1GB
2020-01-17 13:24:45 +01:00
68e225fb45
test/test_targets: update
2020-01-15 13:09:03 +01:00
04017519c8
soc/interconnect/axi: add Wishbone2AXILite
2019-11-20 12:32:22 +01:00
Florent Kermarrec
George Hilliard
Blake Smith
Jędrzej Boczar
Mariusz Glebocki
Pawel Sagan