Commit Graph

9830 Commits

Author SHA1 Message Date
enjoy-digital b11cc8c3eb
Merge pull request #2082 from enjoy-digital/efinix_iface_signal_names
Efinix iface signal names.
2024-09-26 11:42:02 +02:00
Florent Kermarrec 39d292a3c7 build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names. 2024-09-26 10:38:05 +02:00
Florent Kermarrec a3a55fc8fb build/efinix/common: Directly pass ClockSignal/Signal to blocks and let the build resolve names. 2024-09-26 10:14:42 +02:00
Florent Kermarrec fde9d2e4ad build/efinix/efinity: Add resolve_iface_signal_names method to automatically resolve ClockSignal/Signal names passed in the blocks.
Allow the Migen/LiteX build elaboration to resolve signal names and just use it in blocks to avoid name_override workaround.
2024-09-26 10:13:58 +02:00
Dolu1990 c3e87367c3 soc/cores/vexriscv_smp: Add the generation of the default sim config (https://github.com/litex-hub/linux-on-litex-vexriscv/issues/405) 2024-09-25 10:38:37 +02:00
Florent Kermarrec b86d76baed build/sim/core/veril.cpp: Flush trace file on finish, fix issue with empty .fst dumps with short simulations. 2024-09-25 08:56:51 +02:00
Florent Kermarrec c95a6e041c soc/interconnect/stream: Add Delay module. 2024-09-23 12:23:29 +02:00
Florent Kermarrec b2f63b37cc CHANGES.md: Update. 2024-09-20 13:00:40 +02:00
Florent Kermarrec 427ec10cc4 CONTRIBUTORS: Update. 2024-09-20 12:43:18 +02:00
Florent Kermarrec 726d39f40d LICENSE: Bump year. 2024-09-20 12:39:28 +02:00
enjoy-digital baff4c69fe
Merge pull request #2075 from trabucayre/efinix_clkinput_signal
build/efinix/common.py: ClkInput: added ClockSignal support
2024-09-19 11:59:06 +02:00
enjoy-digital 033ec13f08
Merge pull request #2076 from trabucayre/xc7s_jtag
Spartan7 jtag support
2024-09-19 11:53:55 +02:00
Florent Kermarrec 6e9dffdbf5 soc/core/hyperbus: Avoid combinatorial loop on write bursts (Reported when building with Vivado). 2024-09-19 11:10:51 +02:00
Florent Kermarrec ad2c3fcea7 soc/cores/cpu/vexiirscv: Add standard variant to allow compilation without specifying --cpu-variant. 2024-09-19 09:21:13 +02:00
Gwenhael Goavec-Merou f1e1f3530e build/efinix/ifacewriter.py: allows the use of ClockSignal for IN_CLK_PIN (gpio) 2024-09-19 09:14:30 +02:00
Gwenhael Goavec-Merou aca959b059 build/efinix/common.py: ClkInput: added ClockSignal support 2024-09-19 09:12:36 +02:00
Gwenhael Goavec-Merou e072156b93 build/xilinx/platform.py: added xc7s to the list of device supporting jtag access 2024-09-19 06:49:44 +02:00
Gwenhael Goavec-Merou fc68f031a1 soc/cores/jtag.py: added Spartan7 definition for BSCANE2 2024-09-19 06:49:10 +02:00
enjoy-digital 9bacbe130b
Merge pull request #1974 from motec-research/dts_zephyr_updates
DTS zephyr updates
2024-09-17 14:58:51 +02:00
Florent Kermarrec a350d2e909 soc/interconnect/stream: Add optional CSR to Multiplexer/Demultiplexer and Crossbar module with mux and demux. 2024-09-13 19:21:26 +02:00
Florent Kermarrec 2a19a61e05 build/xilinx/vivado: Fix typo. 2024-09-13 10:39:13 +02:00
enjoy-digital 99550809b3
Merge pull request #2069 from VOGL-electronic/fix-sim-ethernet
sim: add HW_PREAMBLE_CRC for ethernet
2024-09-13 08:36:40 +02:00
Florent Kermarrec dc8c1bd9cd build/xilinx/vivado: Rename opt_directive to vivado_opt_directive for consistency with other directives. 2024-09-12 18:04:25 +02:00
Florent Kermarrec 203c9816b2 integration/soc/add_etherbone: Allow 64-bit support now that validated. 2024-09-12 13:39:13 +02:00
Matthias Breithaupt 2fd8c2cd61 sim: add HW_PREAMBLE_CRC for ethernet
This fixes the behavior of `ethernet_phy_model` `"sim"`. As the preamble
is automatically attached by the tap, there is no need to add it from
the BIOS. To let the BIOS know, `HW_PREAMBLE_CRC` needs to be set.

Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-09-12 10:07:43 +02:00
enjoy-digital b41a526e81
Merge pull request #2066 from VOGL-electronic/soc.py_ethernet_mac
soc.py: add_ethernet: add mac addr constant
2024-09-11 11:54:14 +02:00
enjoy-digital 11c7b69fd4
Merge pull request #2065 from VOGL-electronic/bios_little_warning_fix
bios: boot.c: fix warnings
2024-09-11 11:53:52 +02:00
Fin Maaß 7b3f1509d1
soc.py: add_ethernet: add mac addr constant
add mac addr constant to add_ethernet,
so it matches the one from add_etherbone.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-11 11:21:53 +02:00
Fin Maaß 3966e3438c
bios: boot.c: fix warnings
this fixes the warnings, when compiling.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-11 11:15:56 +02:00
Gwenhael Goavec-Merou dc8b74cc58
Merge pull request #2060 from Dolu1990/efinix-rework
build/efinix: add a few IO primitives, IO constraints, sdc rework
2024-09-10 18:40:10 +02:00
Gwenhael Goavec-Merou a80f290d80 soc/cores/clock/efinix.py: fill platform.clks with clkout mapping cd/clk_out_name. litex/build/efinix/ifacewriter.py: generate_lvds: when slow_clk/fast_clk are ClockSignal uses platform.clks to map between domain and signal name 2024-09-10 18:07:34 +02:00
Gwenhael Goavec-Merou ad09ffc150 soc/cores/clock/efinix.py: register_clkin: uses clkin.name_override as input_signal name when name is not provided and PLL is configured in CORE or INTERNAL mode, create_clkout: added PLL name in clk_name str 2024-09-10 18:03:12 +02:00
Gwenhael Goavec-Merou 109ae17e9e build/efinix/common.py: replaced i as str by a ClockDomain 2024-09-10 17:56:49 +02:00
Florent Kermarrec 458e0057f2 soc/interconnect/wishbone: Add Bypass mode on Cache when cachesize == 0 and similar data_widths. 2024-09-09 18:24:14 +02:00
Florent Kermarrec 5cd1a57080 soc/interconnect/wishbone: Cosmetic cleanup on Cache. 2024-09-09 18:16:40 +02:00
enjoy-digital e06045c576
Merge pull request #2059 from Dolu1990/vexii-clk-video
soc/cores/vexiiriscv: update clocks + add video framebuffer support
2024-09-09 14:12:50 +02:00
Dolu1990 2db93c8e78 core/vexiiriscv: improve l2 timings 2024-09-06 16:07:05 +02:00
enjoy-digital a1a3e846ac
Merge pull request #2058 from VOGL-electronic/bios_add_spiram
bios: add spiram
2024-09-06 08:32:11 +02:00
Fin Maaß bd03c496a1 bios: add spiram
add spiram in bios, so it can enable QPI.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-05 16:31:32 +02:00
Dolu1990 599c6dde37
litex/build/efinix/common.py add EfinixDDRTristate binding
Co-authored-by: Fin Maaß <info@finmaass.de>
2024-09-05 16:12:32 +02:00
Dolu1990 c0fddb6561 build/efinix: add a few IO primitives, IO constraints, but mainly it rework how the SDC are handled 2024-09-05 15:21:12 +02:00
Dolu1990 642cfbe9a7 soc/cores/vexiiriscv: update clocks + add video framebuffer support 2024-09-05 15:16:15 +02:00
Dolu1990 e62d84b77b Revert "soc/cores/vexiiriscv: update clocks + add video framebuffer support"
This reverts commit 0ea6dd91aa, reversing
changes made to fa47c62b6d.
2024-09-05 15:15:49 +02:00
Dolu1990 0ea6dd91aa soc/cores/vexiiriscv: update clocks + add video framebuffer support 2024-09-05 15:14:46 +02:00
enjoy-digital fa47c62b6d
Merge pull request #2057 from Dolu1990/usb_ohci_phy_fix2
core/usb_ohci: fix SDRTristate clock
2024-09-05 14:40:34 +02:00
Dolu1990 f512c65077 vexiiriscv git update 2024-09-05 13:17:22 +02:00
Dolu1990 2190ca403a core/usb_ohci: fix SDRTristate clock 2024-09-05 10:24:45 +02:00
Florent Kermarrec f67b39739e soc/integration/add_ethernet: Expose full_memory_we parameter. 2024-09-05 10:18:12 +02:00
Dolu1990 1f2418de3b core/usb_ohci: fix SDRTristate clock 2024-09-05 10:17:22 +02:00
Dolu1990 84e7e816c7 efinix: pll now force the generated clock into cd.clk *WARNING* 2024-09-05 10:16:43 +02:00