Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
8,703 Commits 42 Branches 14 Tags 30 MiB
Commit Graph

8703 Commits

Author SHA1 Message Date
Florent Kermarrec 6b4d5cd3e1 README: Add --config to install command. 2022-01-26 14:51:54 +01:00
Florent Kermarrec af26d939d0 litex_setup: Declare python3 in top and use it. 2022-01-26 14:49:02 +01:00
enjoy-digital f82f769794
Merge pull request #1185 from benstobbs/master 
litex_setup.py on Windows: Change install "python3" to current interpreter
 2022-01-26 14:45:00 +01:00
Florent Kermarrec 4ab45d72a8 litex_setup: Add --status argument to display Git status of repositories. 2022-01-26 14:44:04 +01:00
Florent Kermarrec d2d8d902e1 litex_setup/print_status: Add underline parameter and use it. 2022-01-26 14:20:41 +01:00
Florent Kermarrec 419d605e38 build/toolchains: Specify passed toolchain when unknown. 2022-01-26 11:56:22 +01:00
Ben Stobbs e0149eb814 change repo install python interpreter to current interpreter 2022-01-25 22:46:33 +00:00
enjoy-digital 3020344fd8
Merge pull request #1184 from trabucayre/yosys_nextpnr_zynq 
litex/build/xilinx/yosys_nextpnr: adding zynq7 and xc7z010 & xc7z020 support
 2022-01-25 22:27:01 +01:00
enjoy-digital 7acdac2e51
Merge pull request #1183 from trabucayre/fix_yosys_synth 
litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE
 2022-01-25 22:26:18 +01:00
Gwenhael Goavec-Merou f00fe1b1d8 litex/build/xilinx/yosys_nextpnr: adding zynq7 and xc7z010 & xc7z020 support 2022-01-25 21:58:03 +01:00
Gwenhael Goavec-Merou f8acc5f506 litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE 2022-01-25 21:44:02 +01:00
Florent Kermarrec 77c6cdd78e cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency. 2022-01-25 11:09:15 +01:00
Florent Kermarrec ea6bb3dd80 test/test_clock: Add minimal ECP5Delay test (syntax), rename tests with underscore. 2022-01-25 10:49:33 +01:00
enjoy-digital 6ff8b6e4ed
Merge pull request #1173 from sergachev/ecp5_delay 
clock/lattice_ecp5: add ECP5 dynamic delay DELAYF primitive support
 2022-01-25 10:44:53 +01:00
enjoy-digital d059111c92
Merge pull request #1180 from suarezvictor/master 
Add yosys+nextpnr toolchain support
 2022-01-24 19:02:02 +01:00
Victor Suarez Rovere 6d7f8888ac Add yosys+nextpnr toolchain support 2022-01-24 13:35:12 -03:00
enjoy-digital 6b3eda16f2
Merge pull request #1179 from Technosystem-Labs/vexriscv_hw_breakpoints 
Added Vexriscv hardware breakpoint variants for Mini and Lite.
 2022-01-24 08:16:39 +01:00
Mikolaj Sowinski 9e0d8b3f41 Added Vexriscv hardware breakpoint variants for Mini and Lite. 2022-01-24 00:00:26 +01:00
enjoy-digital 8d3f12ebbd
Merge pull request #1178 from sergachev/gowin_emcu 
Enable LiteX BIOS on Gowin EMCU ARM core
 2022-01-23 21:01:06 +01:00
enjoy-digital 57fef500a7
Merge pull request #1177 from yetifrisstlama/i2c 
bitbang.py: initialize SCL / SDA lines to high on reset
 2022-01-23 21:00:20 +01:00
Ilia Sergachev f36619987b software/bios: update comment 2022-01-23 16:57:33 +01:00
Ilia Sergachev 85f892227a cores/cpu/gowin: re-enable write access to csr bus 2022-01-23 16:34:47 +01:00
Michael Betz e4ceaa7cc2
bitbang.py: initialize SCL / SDA lines to high on reset 
* otherwise might block the I2C bus on reset
 2022-01-23 16:11:34 +01:00
Ilia Sergachev 0f44723957 cores/cpu/gowin: fix isr table optimization and uart init 2022-01-23 15:37:00 +01:00
Ilia Sergachev d4c12a5231 cores/cpu/gowin_emcu: add software support 2022-01-23 11:20:44 +01:00
Ilia Sergachev 3f2a7b9bfd software/bios: set attribute used on main to fix optimization in some configurations 2022-01-23 11:04:22 +01:00
Ilia Sergachev ef5f6398b2 integration/builder: enable bios on gowin emcu 2022-01-23 11:02:36 +01:00
enjoy-digital 0e9e57c926
Merge pull request #1176 from Icenowy/gwpsram 
gowin: add hack for copackaged PSRAM
 2022-01-23 08:33:29 +01:00
Icenowy Zheng b7b054d48e gowin: add hack for copackaged PSRAM 
Some Gowin FPGAs has copackaged "PSRAM" instead of "HyperRAM". They're
in fact also HyperRAM, but named differently and because of this needs
slightly changed hack.

Add hack for PSRAM too. In case of two PSRAM chips are used, the bus is
wider so the needed definition is already in place, so the bus width
hack is not needed.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2022-01-23 03:08:18 +08:00
enjoy-digital 44bea44be3
Merge pull request #1172 from stffrdhrn/or1k-marocchino-linux 
Or1k marocchino linux fixes
 2022-01-21 19:28:56 +01:00
Ilia Sergachev 4b22eda662 clock/lattice_ecp5: add ECP5 dynamic delay DELAYF primitive support 2022-01-21 14:05:28 +01:00
Florent Kermarrec 443faef33b litex_sim: Update SPI Flash support. 2022-01-21 10:05:07 +01:00
Florent Kermarrec bcc9c14c7e cores/cpu: Fix automatic collection for Rocket/BlackParrot/EOS-S3. 2022-01-20 17:44:35 +01:00
Stafford Horne d1746e1286 tools/litex_json2dts_linux.py: Support DTS generator for OpenRISC marocchino 
Marocchino is also a or1k architecture and the DTS file is the same
as mor1kx.  I would like to use the dts generator for marocchino too.

This patch introduces a new mapping to derive architecture based on the
cpu_name it then uses the cpu_arch (architecture) to control the DTS
generation rather than the cpu name.
 2022-01-20 20:42:15 +09:00
Stafford Horne d3942c137d bios/boot: Support setting EVBAR for Marocchino too 
The Marocchino CPU is an OR1K architecture so it also requires setting
of EVBAR to boot linux.
 2022-01-20 20:35:53 +09:00
Florent Kermarrec a76828a40a soc/add_uart: Fix uart_name="uartbone" case. 2022-01-20 10:23:06 +01:00
enjoy-digital 928ee285dc
Merge pull request #1171 from enjoy-digital/out-of-tree-cpus 
Simplify CPUs collection and add out-of-tree support.
 2022-01-20 09:46:43 +01:00
Florent Kermarrec 681f474c66 CHANGEs: Update. 2022-01-20 09:25:49 +01:00
Florent Kermarrec bdc22770e9 cores/cpu: Deprecate external CPU class support (advantageously replaced by out-of-tree support which is more flexible). 2022-01-20 09:25:39 +01:00
Florent Kermarrec c675acb868 cores/cpu: Add out-of-tree CPUs support (By searching CPUs in execution directory). 2022-01-20 09:18:10 +01:00
Florent Kermarrec ba14212129 cores/cpu: Avoid duplication between CPU_GCC_TRIPLE_RISCV64/CPU_GCC_TRIPLE_RISCV32, CPU_GCC_TRIPLE_RISCV32 is just an extension of CPU_GCC_TRIPLE_RISCV64. 2022-01-20 08:49:58 +01:00
Florent Kermarrec 576b96ba83 cores/cpu: Switch to automatic CPUs collection. 
Simplify code/maintenance and will also enable out-of-tree CPUs support.
 2022-01-20 08:39:22 +01:00
Florent Kermarrec 02fe32bd79 tools/litex_server/sim: Deprecate bridge use in favor of crossover (was already supported). 2022-01-19 16:54:56 +01:00
Florent Kermarrec f5e1f1c05b soc/add_uart: Add list of supported UARTs, reorder and add error message when not supported/found. 2022-01-19 16:40:30 +01:00
Florent Kermarrec 3683c5b866 build/sim/platform: Add loose support to request. 2022-01-19 16:39:32 +01:00
Florent Kermarrec 11e8a3ce23 soc/add_uart: Simplify/Cleanup. 2022-01-19 16:06:55 +01:00
Florent Kermarrec fda3164be4 soc/add_uart: Separate name/uart_name to allow multiple UARTs in the same design. 2022-01-19 15:48:42 +01:00
Florent Kermarrec 6d697f4506 soc/add_etherbone: Improve genericity to allow multiple instances of Etherbone cores. 
ex:
    self.submodules.ethphy0 = LiteEthPHYMII(
        clock_pads = self.platform.request("eth_clocks", 0),
        pads       = self.platform.request("eth", 0))
    self.submodules.ethphy1 = LiteEthPHYMII(
        clock_pads = self.platform.request("eth_clocks", 1),
        pads       = self.platform.request("eth", 1))
    self.add_etherbone(name="etherbone0", phy=self.ethphy0, phy_cd="ethphy0_eth")
    self.add_etherbone(name="etherbone1", phy=self.ethphy1, phy_cd="ethphy1_eth")
 2022-01-19 15:07:55 +01:00
enjoy-digital 2a17214813
Merge pull request #1169 from sergachev/fix/zynq_software 
Fix Zynq software support
 2022-01-19 10:04:48 +01:00
Florent Kermarrec 2f433611dd litex_sim: Add .json support for --rom/ram/sdram-init. 2022-01-19 09:58:38 +01:00