Sebastien Bourdeauducq
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68cd445662
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bus/wishbone2asmi: fix cache tag size
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2012-05-15 15:18:03 +02:00 |
|
Sebastien Bourdeauducq
|
0bea1e2589
|
asmi: dat_wm high to disable data write
|
2012-05-15 14:41:54 +02:00 |
|
Sebastien Bourdeauducq
|
f2c20e4af0
|
bus/asmibus/hub: hack to prevent comb loops
|
2012-04-30 17:11:42 -05:00 |
|
Sebastien Bourdeauducq
|
398ece8fe2
|
fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
|
2012-04-30 16:38:40 -05:00 |
|
Sebastien Bourdeauducq
|
0b62e573ae
|
sim: pass extra keyword arguments to Verilog converter
|
2012-04-30 16:38:17 -05:00 |
|
Sebastien Bourdeauducq
|
6a52e44d09
|
fhdl: support len() on signals
|
2012-04-08 18:06:22 +02:00 |
|
Sebastien Bourdeauducq
|
b9c533be51
|
bank/csrgen: allow specifying existing CSR interface
|
2012-04-06 14:59:09 +02:00 |
Brandon Hamilton
|
49b58a03a0
|
Optionally accept iverilog simulator options
|
2012-04-03 12:58:19 +02:00 |
|
Sebastien Bourdeauducq
|
2a4e49e381
|
fhdl: phase out pads
|
2012-04-02 19:21:43 +02:00 |
|
Sebastien Bourdeauducq
|
1b60c7ff40
|
vpi: delete merged Icarus Verilog patch
|
2012-04-02 19:11:32 +02:00 |
|
Sebastien Bourdeauducq
|
623e8e436a
|
fhdl/verilog: do not attempt to initialize instance and mem output signals
|
2012-04-02 12:59:42 +02:00 |
|
Sebastien Bourdeauducq
|
6e3b25ebb6
|
bus/dfi: reset active low signals to 1
|
2012-04-01 17:43:24 +02:00 |
|
Sebastien Bourdeauducq
|
d3c6b8d16f
|
sim/proxy: support lists
|
2012-04-01 17:19:53 +02:00 |
|
Sebastien Bourdeauducq
|
f3ae22f488
|
fhdl/verilog: initialize internal read-only signals with their reset values
|
2012-04-01 16:39:11 +02:00 |
|
Sebastien Bourdeauducq
|
0dfc215fe8
|
corelogic/roundrobin: handle correctly special case with 1 request source
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2012-03-31 18:01:40 +02:00 |
|
Sebastien Bourdeauducq
|
94b02aa8ed
|
bus/asmicon: initiator
|
2012-03-30 22:16:31 +02:00 |
|
Sebastien Bourdeauducq
|
bb864c65dc
|
sim: proxy
|
2012-03-30 16:40:26 +02:00 |
|
Sebastien Bourdeauducq
|
081b658e2d
|
Update copyright notices
|
2012-03-23 16:41:30 +01:00 |
|
Sebastien Bourdeauducq
|
d47b564fad
|
corelogic/fsm: typo
|
2012-03-18 22:12:46 +01:00 |
|
Sebastien Bourdeauducq
|
5f28103769
|
corelogic/fsm: delayed enters
|
2012-03-18 00:09:40 +01:00 |
|
Sebastien Bourdeauducq
|
a4294762d0
|
corelogic/roundrobin: CE switching
|
2012-03-16 16:54:47 +01:00 |
|
Sebastien Bourdeauducq
|
e969b9afc3
|
corelogic: convert timeline to function and move to misc
|
2012-03-15 20:25:44 +01:00 |
|
Sebastien Bourdeauducq
|
1665f293a6
|
bus/asmibus/hub: require finalization before get_slots
|
2012-03-14 16:19:29 +01:00 |
|
Sebastien Bourdeauducq
|
5c0cc6292c
|
fhdl: export log2_int
|
2012-03-14 12:19:42 +01:00 |
Alain Péteut
|
97fece249d
|
setup.py: simplify
Signed-off-by: Alain Péteut <alain.peteut@yahoo.com>
|
2012-03-11 00:52:13 +01:00 |
|
Sebastien Bourdeauducq
|
f6e76ae198
|
doc: more examples and comments
|
2012-03-10 19:38:39 +01:00 |
|
Sebastien Bourdeauducq
|
1f4c58ee26
|
doc: cosmetic changes (thanks sh4rm4 for reporting typos)
|
2012-03-10 17:59:42 +01:00 |
|
Sebastien Bourdeauducq
|
78c707e354
|
doc: use script font
|
2012-03-09 21:57:50 +01:00 |
|
Sebastien Bourdeauducq
|
7b1101ab99
|
doc: simulation
|
2012-03-09 21:17:21 +01:00 |
|
Sebastien Bourdeauducq
|
0165d23295
|
doc: cosmetic changes (thanks rofl0r for reporting typos)
|
2012-03-09 18:26:00 +01:00 |
|
Sebastien Bourdeauducq
|
59db4e9106
|
doc: add logo
|
2012-03-09 17:16:33 +01:00 |
|
Sebastien Bourdeauducq
|
90546fd811
|
doc: switch to sphinx
|
2012-03-09 17:08:38 +01:00 |
|
Sebastien Bourdeauducq
|
57a87b3316
|
examples: FIR filter simulation
|
2012-03-08 20:49:36 +01:00 |
|
Sebastien Bourdeauducq
|
bfcd4e636b
|
fhdl: handle negative constants correctly
|
2012-03-08 20:49:24 +01:00 |
|
Sebastien Bourdeauducq
|
f4adb0fe9c
|
examples: remove outdated wb_intercon simulation
|
2012-03-08 18:17:56 +01:00 |
|
Sebastien Bourdeauducq
|
84aa703447
|
vpi: support extra include directories
|
2012-03-08 18:14:40 +01:00 |
|
Sebastien Bourdeauducq
|
bbaadebf68
|
gitignore: update
|
2012-03-08 18:14:19 +01:00 |
|
Sebastien Bourdeauducq
|
ab800fa2ed
|
bus: generic transaction model
|
2012-03-08 18:14:06 +01:00 |
|
Sebastien Bourdeauducq
|
ddc0e49981
|
vpi: patch for Icarus Verilog
|
2012-03-08 17:27:59 +01:00 |
|
Sebastien Bourdeauducq
|
59a57e7a76
|
examples: small cleanup
|
2012-03-08 15:55:02 +01:00 |
|
Sebastien Bourdeauducq
|
678a89d572
|
sim: fix zero encoding
|
2012-03-08 15:34:08 +01:00 |
|
Sebastien Bourdeauducq
|
decbd069fa
|
sim: fix message debug formatting
|
2012-03-08 15:27:35 +01:00 |
|
Sebastien Bourdeauducq
|
98e96b3952
|
sim: make initialization cycle optional (selectable by function attribute)
|
2012-03-06 19:43:59 +01:00 |
|
Sebastien Bourdeauducq
|
8160ced2e9
|
sim: memory access
|
2012-03-06 19:29:39 +01:00 |
|
Sebastien Bourdeauducq
|
db8f8bf2e3
|
fhdl: register memory objects with namespace
|
2012-03-06 18:33:44 +01:00 |
|
Sebastien Bourdeauducq
|
6f829c7afc
|
sim: support for signed numbers
|
2012-03-06 16:46:18 +01:00 |
|
Sebastien Bourdeauducq
|
90184b22d2
|
fhdl/verilog: fix signed constant conversion
|
2012-03-06 16:45:44 +01:00 |
|
Sebastien Bourdeauducq
|
0a23cadd38
|
vpi: install target
|
2012-03-06 15:51:09 +01:00 |
|
Sebastien Bourdeauducq
|
9da512dbf5
|
sim: VCD generation
|
2012-03-06 15:26:04 +01:00 |
|
Sebastien Bourdeauducq
|
22b3c11b93
|
sim: clean startup/shutdown
|
2012-03-06 15:00:02 +01:00 |