Sebastien Bourdeauducq
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1794b45ed3
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doc/dataflow: remove ActorNode
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2013-02-10 19:03:18 +01:00 |
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Sebastien Bourdeauducq
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f2665efbfe
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doc/dataflow: remove ALA
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2013-02-10 18:57:03 +01:00 |
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Sebastien Bourdeauducq
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b988003878
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doc: multiple clock domains
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2013-02-10 18:56:45 +01:00 |
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Sebastien Bourdeauducq
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6bca9c8b98
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doc: do not inline examples as this never works with most Sphinx setups ...
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2013-02-10 18:45:06 +01:00 |
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Sebastien Bourdeauducq
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3f063db281
|
doc: update to new Migen APIs
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2013-02-10 18:42:47 +01:00 |
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Sebastien Bourdeauducq
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92b67df41c
|
sim: default runner to Icarus Verilog
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2013-02-09 17:04:53 +01:00 |
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Sebastien Bourdeauducq
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bd6856ba7a
|
flow/perftools: finish removing ActorNode
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2013-02-09 17:03:48 +01:00 |
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Sebastien Bourdeauducq
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473fd20f8c
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fhdl/structure: store clock domain name
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2013-01-24 13:49:49 +01:00 |
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Sebastien Bourdeauducq
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3201554f76
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fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
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2013-01-23 15:13:06 +01:00 |
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Sebastien Bourdeauducq
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314a6c7743
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corelogic: complex arithmetic support
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2013-01-05 14:18:36 +01:00 |
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Sebastien Bourdeauducq
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badba89686
|
fhdl: support nested statement lists
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2013-01-05 14:18:15 +01:00 |
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Sebastien Bourdeauducq
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47f5fc70e4
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pytholite: fix bug with constant assignment to register
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2012-12-19 16:21:57 +01:00 |
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Sebastien Bourdeauducq
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9c65402fda
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pytholite: prune unused registers
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2012-12-19 16:03:05 +01:00 |
|
Sebastien Bourdeauducq
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3fae6c8f03
|
Do not use super()
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2012-12-18 14:54:33 +01:00 |
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Sebastien Bourdeauducq
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4d0db2cb05
|
examples/pytholite: fix imports
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2012-12-16 20:26:23 +01:00 |
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Sebastien Bourdeauducq
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b06fbdedd6
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fhdl/tools: bitreverse
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2012-12-14 23:56:16 +01:00 |
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Sebastien Bourdeauducq
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1f350adf14
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actorlib/sim/SimActor: do not drive busy low when generator yields None
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2012-12-14 23:56:03 +01:00 |
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Sebastien Bourdeauducq
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a67f483f0f
|
Token: support idle_wait
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2012-12-14 19:16:22 +01:00 |
|
Sebastien Bourdeauducq
|
6f99241585
|
Move Token to migen.flow.transactions
|
2012-12-14 15:55:38 +01:00 |
|
Sebastien Bourdeauducq
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28b4d99d31
|
replace some forgotten is_abstract()
|
2012-12-12 22:36:45 +01:00 |
|
Sebastien Bourdeauducq
|
a7227d7d2b
|
Remove ActorNode
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2012-12-12 22:20:48 +01:00 |
|
Sebastien Bourdeauducq
|
8163ed4828
|
Merge branch 'master' of github.com:milkymist/migen
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2012-12-06 20:57:30 +01:00 |
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Sebastien Bourdeauducq
|
483b821342
|
fhdl/structure: do not create Signal in Instance when parameter is int
|
2012-12-06 20:56:46 +01:00 |
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Sebastien Bourdeauducq
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280a87ea69
|
elsewhere: do not create interface in default param
|
2012-12-06 17:34:48 +01:00 |
|
Sebastien Bourdeauducq
|
62187aa23d
|
migen/bank: do not create interface in default param
|
2012-12-06 17:28:28 +01:00 |
|
Sebastien Bourdeauducq
|
c3fdf42825
|
bus/csr: add SRAM
|
2012-12-06 17:16:17 +01:00 |
|
Sebastien Bourdeauducq
|
e89c66bf14
|
bank/csrgen: interface -> bus
|
2012-12-06 17:15:34 +01:00 |
|
Sebastien Bourdeauducq
|
273d9d285b
|
bank/description: define reset value of read signal
|
2012-12-05 16:40:44 +01:00 |
|
Sebastien Bourdeauducq
|
34ce934809
|
actorlib/sim: drive busy high until generator is finished
|
2012-12-05 16:40:12 +01:00 |
|
Sebastien Bourdeauducq
|
4bcb39699b
|
bus/wishbone/sram: accept memories < 32 bits
|
2012-12-01 13:04:22 +01:00 |
|
Sebastien Bourdeauducq
|
523816982a
|
bus/wishbone: add SRAM
|
2012-12-01 12:59:09 +01:00 |
|
Sebastien Bourdeauducq
|
adb1565d7a
|
pytholite: fix bit width of selection signal
|
2012-11-30 17:07:32 +01:00 |
|
Sebastien Bourdeauducq
|
cfb23c442f
|
pytholite: support signed registers
|
2012-11-30 17:07:12 +01:00 |
|
Sebastien Bourdeauducq
|
7093939309
|
corelogic/roundrobin: fix request width (again)
|
2012-11-29 23:47:51 +01:00 |
|
Sebastien Bourdeauducq
|
31c722f993
|
corelogic/roundrobin: fix request width
|
2012-11-29 23:47:08 +01:00 |
|
Sebastien Bourdeauducq
|
70e97e0456
|
Fix various errors from new bitwidth/signedness system conversion
|
2012-11-29 23:36:55 +01:00 |
|
Sebastien Bourdeauducq
|
261166d92b
|
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
|
2012-11-29 22:59:54 +01:00 |
|
Sebastien Bourdeauducq
|
55d143a454
|
fhdl/structure: add unary minus
|
2012-11-29 22:52:57 +01:00 |
|
Sebastien Bourdeauducq
|
d8e478efee
|
Replace Signal(bits_for(... with Signal(max=...
|
2012-11-29 21:53:36 +01:00 |
|
Sebastien Bourdeauducq
|
50ed73c937
|
New specification for width and signedness
|
2012-11-29 21:22:38 +01:00 |
|
Sebastien Bourdeauducq
|
6eebfce44a
|
Refactor Case
|
2012-11-29 01:11:15 +01:00 |
|
Sebastien Bourdeauducq
|
070652cc39
|
pytholite/reg: use source id in dictionary
|
2012-11-29 00:09:35 +01:00 |
|
Sebastien Bourdeauducq
|
fee22a4631
|
Remove Constant
|
2012-11-28 23:18:43 +01:00 |
|
Sebastien Bourdeauducq
|
2a3ef28041
|
examples/sim/dataflow: update to new APIs
|
2012-11-28 22:44:14 +01:00 |
|
Sebastien Bourdeauducq
|
39d577d65e
|
examples/dataflow/dma: update to new APIs
|
2012-11-28 22:42:01 +01:00 |
|
Sebastien Bourdeauducq
|
7c4b5931bc
|
examples/basic: remove unroll example
|
2012-11-28 22:16:02 +01:00 |
|
Sebastien Bourdeauducq
|
59831e0485
|
fhdl/structure: improved bits_for function
|
2012-11-28 18:39:44 +01:00 |
|
Sebastien Bourdeauducq
|
11b1e53224
|
visit/NodeTransformer: copy most nodes
|
2012-11-28 17:50:55 +01:00 |
|
Sebastien Bourdeauducq
|
a2bcbfdf8f
|
fhdl/tools: use NodeTransformer to lower arrays
|
2012-11-28 17:46:15 +01:00 |
|
Sebastien Bourdeauducq
|
5440fa715c
|
examples/basic/arrays: add array assignment to fragment
|
2012-11-26 22:47:35 +01:00 |