Florent Kermarrec
737ed9d658
setup: remove litex_simple setup from entry points.
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Now provided by LiteX-Boards: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/simple.py
2021-01-12 17:21:26 +01:00
William D. Jones
ce243820fe
tools/litex_term: Convert some common scan codes into ANSI codes on Windows.
2021-01-11 21:02:37 -05:00
William D. Jones
5babcadbed
tools/litex_term: Set ENABLE_VIRTUAL_TERMINAL_PROCESSING flag on Windows.
2021-01-11 19:54:21 -05:00
William D. Jones
bfc624f23e
tools/litex_term: Avoid importing termios and pty on Windows.
2021-01-11 14:51:55 -05:00
Florent Kermarrec
460fada3ac
tools/litex_term: revert LiteXTerm to threading (multiprocessing breaks Windows/OS-X).
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Ideally we should switch to AsyncIO as some point.
2021-01-11 19:29:15 +01:00
Florent Kermarrec
1ce194007b
software: allow BIOS compilation with UART disabled.
2021-01-08 19:18:44 +01:00
Florent Kermarrec
19fda3364a
tools/litex_term: fix 100% cpu load after refactoring (thanks sergpolkin).
2021-01-08 13:57:33 +01:00
Florent Kermarrec
5f9c4a4ab4
soc/cores/gpio: remove intermediate _pads signal.
2021-01-06 21:39:02 +01:00
Florent Kermarrec
0984308318
cores/gpio: add assertion on pads (has to be a Signal).
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Due to the bi-directional nature of tristate, Cat is not supported (so also
not platform.request_all).
2021-01-06 09:56:56 +01:00
enjoy-digital
8109806609
Merge pull request #768 from davidlattimore/nx-320kb-ram
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Lattice NX: Allow up to 320KB of RAM
2021-01-06 08:55:27 +01:00
David Lattimore
875f34f8e2
Lattice NX: Allow up to 320KB of RAM
2021-01-06 09:45:08 +11:00
Florent Kermarrec
16008d3f3a
cpu/vexriscv/cpu-count: fix type and add comment (thanks dayjaby).
2021-01-04 14:43:08 +01:00
Florent Kermarrec
f31f9a20f0
boards: remove and switch to litex_boards.
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Keeping board definition files directly in LiteX is no longer useful since we are already relying on board
definitions files from LiteX-Boards (https://github.com/litex-hub/litex-boards ) in various benches/projects
and having definitions files directly in LiteX creates confusion/additional work.
For projects using board definition files from LiteX, the litex.boards import can just be replaced with litex_boards:
from litex.boards.platforms import kc705
from litex_boards.platforms import kc705
2021-01-04 14:09:35 +01:00
enjoy-digital
afbac26e80
Merge pull request #754 from cr1901/picorv32-riscv32
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Use riscv32 gcc triples for picorv32- superset of riscv64 triples.
2020-12-31 09:32:31 +01:00
William D. Jones
f65491c809
Use riscv32 gcc triples for picorv32- superset of riscv64 triples.
2020-12-31 03:22:56 -05:00
Florent Kermarrec
737952577b
Changes: update/release.
2020-12-30 16:49:15 +01:00
Florent Kermarrec
b9e0c95c18
cpu/microwatt: use 0xf9807b6 and fix compilation, working with IRQs :)
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Tested with:
/arty.py --cpu-type=microwatt --cpu-variant=standard+irq --integrated-rom-size=0x10000 --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Dec 30 2020 15:59:16
BIOS CRC passed (fb76e85d)
Migen git sha1: d42aa6f
LiteX git sha1: 74844db3
--=============== SoC ==================--
CPU: Microwatt @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 262144KiB 16-bit @ 800MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write latency calibration:
m0:0 m1:0
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000011111111111111100000| delays: 19+-07
m0, b2: |00000000000000000000000000001111| delays: 30+-02
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b01 delays: 19+-07
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000011111111111111000000| delays: 19+-07
m1, b2: |00000000000000000000000000001111| delays: 30+-01
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b01 delays: 19+-06
Switching SDRAM to hardware control.
Memtest at 0x0000000040000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x0000000040000000 (2MiB)...
Write speed: 32MiB/s
Read speed: 54MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2020-12-30 16:20:20 +01:00
Florent Kermarrec
74844db3b9
cores/cpu: add optional add_soc_components method and use it to add VexRiscv-SMP's PLIC/CLINT and Microwatt's XCIS.
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Also shorten XCIS name on Microwatt from HOSTXICS to XCIS.
2020-12-30 15:35:27 +01:00
Florent Kermarrec
49217ec6ea
cores/cpu/vexriscv_smp: minor cleanups.
2020-12-30 14:45:33 +01:00
Florent Kermarrec
a8ddbb190a
cores/cpu/vexriscv_smp: add standard variant (similar to Linux, avoid passing cpu-variant=linux when selection vexriscv_smp).
2020-12-30 14:41:54 +01:00
Florent Kermarrec
7bcebf4cdd
cpu/microwatt: improve/fix XICS controller integration for variants with irq.
2020-12-30 12:25:01 +01:00
Florent Kermarrec
0cba91022e
cpu/vexriscv_smp: move smp_slave to crt0. Fixes bare metal demo compilation with VexRiscv-SMP.
2020-12-30 11:56:11 +01:00
Florent Kermarrec
4f6bc32a5a
software/demo: make leds optional.
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Allow running demo directly with litex_sim:
litex_sim (then exit with ctrl-c on BIOS prompt)
litex_bare_metal_demo --build-path=build/sim/
litex_sim --ram-init=demo.bin
2020-12-30 11:25:32 +01:00
Florent Kermarrec
052a76f253
README: update example projects built with the tools, remove 2020.04 note.
2020-12-30 11:06:55 +01:00
Florent Kermarrec
3e115a0ecb
CHANGES: update.
2020-12-30 09:06:36 +01:00
Florent Kermarrec
db5f017341
README: add link LiteX-Boards in ecosystem table.
2020-12-30 08:37:11 +01:00
Florent Kermarrec
8ff26b7304
targets/arty: add variant support through --variant argument.
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./arty.py --variant=a7-35 or a7-100
2020-12-29 18:45:41 +01:00
Florent Kermarrec
70d364cf4e
integration/soc: add software_debug parameter to add_ethernet, add_(spi)sdcard to ease enabling software debug traces from design.
2020-12-29 15:38:46 +01:00
Florent Kermarrec
c7056b77bb
tools/litex_json2dts/soc_controller: remove VexRiscv-SMP workaround now that we able to use upstream linux litex patches.
2020-12-29 12:25:38 +01:00
Florent Kermarrec
7627dadb9b
tools/litex_json2dts/soc_controller: add workaround for VexRiscv-SMP.
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We need to fix https://github.com/litex-hub/linux-on-litex-vexriscv/issues/176
to be able to switch to soc-controller with VexRiscv-SMP.
2020-12-29 09:29:23 +01:00
enjoy-digital
d5bf09d8f4
Merge pull request #747 from shenki/soc-controller-compatible
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dts: Fix soc controller compatible
2020-12-29 09:23:03 +01:00
Florent Kermarrec
bf32d23d9a
tools/litex_json2dts: add --polling args to allow forcing polling mode on peripherals.
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Can be useful for debug purpose or bring up of new hardware not yet supporting IRQs.
2020-12-29 09:03:35 +01:00
Florent Kermarrec
d9a44ce10f
tools/litex_json2dts: minor changes/cleanup on #745 .
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- shorten args description.
- avoid mixing initrd_start/initrd_start_offset: just use initrd_start and indicate it's relative.
- others minor cleanups.
2020-12-29 08:36:55 +01:00
enjoy-digital
152ae03798
Merge pull request #745 from stffrdhrn/dts-interrupts
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RFC dts: Support generating interrupt config
2020-12-29 08:16:19 +01:00
enjoy-digital
cf9ea62193
Merge pull request #749 from stffrdhrn/dts-initrd-size
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dts: Allow specifying initrd position and size via args
2020-12-29 08:09:15 +01:00
Stafford Horne
a2c9b17959
dts: Allow specifying initrd position and size via args
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This is needed as my initrd size is much larger than the default 8mb.
Also, sometimes the kernel I build is also large, so its good to be
able to move the initrd starting position.
Issue #748
2020-12-29 08:18:55 +09:00
Stafford Horne
5cc2c4aaf7
dts: Support generating interrupt config
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This addresses #744
2020-12-28 09:51:22 +09:00
Joel Stanley
13345bfe7f
dts: Fix soc controller compatible
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The version that landed upstream is spelt litex,soc-controller with a
dash instead of an underscore.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-12-27 22:40:29 +10:30
enjoy-digital
bddb170650
Merge pull request #742 from rprinz08/master
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Enable etherbone usage on multiple ethernet interfaces
2020-12-23 10:44:40 +01:00
rprinz08
c99c96bc68
Enable etherbone usage on multiple ethernet interfaces
2020-12-22 21:13:10 +01:00
Florent Kermarrec
1a338b602a
software/bios: add new mem_list command to list available memory regions.
...
This is useful to know the memory regions available and use the mem_xy commands
on them:
List the memory regions:
litex> mem_list
Available memory regions:
ROM 0x00000000 0x8000
SRAM 0x01000000 0x2000
MAIN_RAM 0x40000000 0x10000000
CSR 0x82000000 0x10000
Test 0x1000 bytes of MAIN_RAM:
litex> mem_test 0x40000000 0x1000
Memtest at 0x40000000 (4KiB)...
Write: 0x40000000-0x40001000 4KiB
Read: 0x40000000-0x40001000 4KiB
Memtest OK
Test speed on 0x1000 bytes of MAIN_RAM:
litex> mem_speed 0x40000000 0x1000
Memspeed at 0x40000000 (4KiB)...
Write speed: 352KiB/s
Read speed: 288KiB/s
2020-12-22 19:15:57 +01:00
Tim Ansell
b3a0b4b60d
Merge pull request #737 from stffrdhrn/or1k-linux-insns
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mor1kx: Enable rotate, fpu and sign extensions under linux
2020-12-22 09:40:53 -08:00
Stafford Horne
3067c57080
mor1kx: Enable gcc compiler flag for cmov
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We enable this instruction so use it.
2020-12-22 22:10:42 +09:00
Stafford Horne
51327e00b5
mor1kx: Enable rotate, sign extend under linux, new fpu extension
...
My thought is that if we are running linux the FPGA should be able to
handle these extra instruction's footprint. Also, since we are running
on linux there may be any kind of software running on the CPU, so allow
handling these instructions.
FPU is added bia a new +fpu extension.
But really, I am running GLIBC tests and they run faster with this
enabled.
2020-12-22 22:10:42 +09:00
Florent Kermarrec
d90d3e043b
software/liblitedram: add optional SDRAM_TEST_DISABLE that can be defined to full disable SDRAM test.
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This is useful in simulation where SDRAM contents is pre-initialized from files (ex Linux-on-LiteX-Vexriscv).
2020-12-22 10:50:15 +01:00
Florent Kermarrec
12dabde77c
integration/soc/add_ethernet: add phy_cd parameter to allow and demonstrate multiple PHYs support.
2020-12-22 09:03:00 +01:00
Florent Kermarrec
c79135c573
software/demo: add litex_bare_metal_demo pre-installed script.
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Build demo: litex_bare_metal_demo --build-path=build/arty/
2020-12-21 19:27:21 +01:00
Florent Kermarrec
4df56ed456
software/demo: add short README.
2020-12-21 18:44:10 +01:00
Florent Kermarrec
ef2ed8bbbc
tools/litex_json2dts: fix vexriscv-smp cpu reg numbering.
2020-12-21 18:16:44 +01:00
Florent Kermarrec
5ec5554713
tools/litex_json2dts: cleanup and reorganize peripherals.
2020-12-21 16:11:45 +01:00