Commit Graph

7329 Commits

Author SHA1 Message Date
developandplay c36e2ae4e8 Add imafd support 2021-07-27 00:44:32 +02:00
developandplay 6ba514ee96 Separate BlackParrot code from adapter code 2021-07-27 00:43:09 +02:00
enjoy-digital 3387853b6b
Merge pull request #977 from antmicro/jboc/gtkw-endpoint
GTKWSave: improved support for Endpoint
2021-07-26 15:01:49 +02:00
Filip Kokosinski 0a0e337754 soc: software: liblitespi: enter QPI mode when using MX25L12833F 2021-07-26 14:32:56 +02:00
Florent Kermarrec 1ce48a973b clock/lattice_ecp5: Fix and rework 4-output solver implementation.
The implementation was causing regressions on actual designs, rework done:
- Only keep a common iteration loop as before.
- Add iteration on CLKO dividers (to fall in the VCO range).
- Do the iterations as before, if while doing it we find a clock suitable for feedback: just use it.
- If no feedback clock has been found: create it (if at least one free output available, if not raise an error).
2021-07-26 14:00:00 +02:00
Jędrzej Boczar 4636a841d3 build/sim/gtkwave: automate handling of Endpoint and other stream primitives 2021-07-22 15:49:20 +02:00
enjoy-digital 751e99690e
Merge pull request #965 from thirtythreeforty/ecp5-pll-x4
ECP5PLL: implement 4-output solver
2021-07-21 19:08:18 +02:00
enjoy-digital a782596513
Merge pull request #975 from cklarhorst/master
soc/add_sdcard: Fix IRQ code, only add IRQs depending on mode
2021-07-21 11:57:21 +02:00
Christian Klarhorst e17a010866 soc/add_sdcard: Fix IRQ code, only add IRQs depending on mode 2021-07-20 22:08:36 +02:00
Florent Kermarrec c64c6e4056 cpu/blackparrot: Re-map csr and keep the lower 128MBs for the SoC IO auto-allocation. 2021-07-20 12:05:54 +02:00
enjoy-digital 1bf7abfc8a
Merge pull request #970 from trabucayre/openfpgaloader_check_type
openfpgaloader: improves freq conversion type
2021-07-19 09:58:21 +02:00
Gwenhael Goavec-Merou e3f577e0be openfpgaloader: improves freq conversion type 2021-07-17 17:02:22 +02:00
Florent Kermarrec e0d5a7bff5 interconnect/packet/Packetizer/Depacketizer: Avoid generating unaligned logic when aligned. 2021-07-15 19:00:50 +02:00
Florent Kermarrec 0a919e709f interconnect/packet: Improve PacketFIFO to handle payload/param separately.
Useful to save resources and store Stream's params more efficiently.
2021-07-15 18:06:03 +02:00
Florent Kermarrec b2f8fa5464 gen/fhdl/verilog: Make DummyAttrTranslate a dict. 2021-07-15 16:48:24 +02:00
enjoy-digital bf52c1083f
Merge pull request #969 from trabucayre/openfpgaloader_add_cable_and_freq_options
openfpgaloader: add cable and freq options
2021-07-15 12:18:01 +02:00
Florent Kermarrec 730b57d9cd build/gowin: Add initial timing constraints support. 2021-07-15 11:06:03 +02:00
Florent Kermarrec 10ea45da55 build/microsemi/common: Cleanup MicrosemiPolarfireAsyncResetSynchronizerImpl. 2021-07-15 10:01:52 +02:00
Florent Kermarrec 2b393254da build: Simplify attr_translate (Now automatically defaults to None when not explicitely listed).
Most of the attributes are Xilinx specific, it does not make sense to provide them on other FPGA devices.
2021-07-15 09:59:15 +02:00
Florent Kermarrec bdc32171fd gen/fhdl/verilog/_printattr: Avoid trying translating attribute when not supported by Toolchain. 2021-07-15 09:57:15 +02:00
Florent Kermarrec 4fd974be10 build/gowin: Minor cleanups. 2021-07-15 09:36:41 +02:00
Gwenhael Goavec-Merou 3706ed7416 openfpgaloader.py: cast int to str 2021-07-14 17:50:50 +02:00
Gwenhael Goavec-Merou c984a4dbc8 openfpgaloader: add cable and freq options 2021-07-14 16:48:29 +02:00
Florent Kermarrec 756503ab92 clock/gowin_gw1n: Add Initial On-Chip Oscillator support.
Ex: self.submodules.osc = GW1NOSC(device="GW1N9K", freq=10e6)
2021-07-14 11:42:35 +02:00
Florent Kermarrec 6fc87f7c85 build/gowin/common: Add DDRInput/DDROutput implementations. 2021-07-14 10:01:54 +02:00
Florent Kermarrec a8cea15b95 cores/clock/gowin_gw1n/create_clkout: Add reset support (through AsyncResetSynchronizer) and enable it by default.
Should be based on PLL's lock but does not seem stable, so use reset input for now.
2021-07-14 09:38:23 +02:00
Florent Kermarrec cfbc06c297 build/gowin/common: Add AsyncResetSynchronizer implementation. 2021-07-14 09:37:00 +02:00
enjoy-digital fab6512928
Merge pull request #967 from JosephBushagour/jbushagour_assembly_interoperability
Make "generated/soc.h" able to be included in assembly files.
2021-07-13 10:47:59 +02:00
enjoy-digital df67b65a0a
Merge pull request #957 from pftbest/fix_fst
Fix compile error when FST traces are enabled on macOS.
2021-07-13 10:38:40 +02:00
Joey Bushagour c79e428fe1 Add soc.h interoperability with assembly. 2021-07-12 08:33:17 -05:00
Florent Kermarrec bc77aa37f0 include/hw/common: Fix _csr_rd_buf/_csr_wr_buf for sizeof(buf[0]) < CSR_DW_BYTES case.
- Shift in _csr_rd_buf should only been done when buf is set.
- When CSR size is not an exact multiple of the CSR data-width, the gap is in
the low addresses, not the high ones. So offset is introduced to take this into
account.
2021-07-09 17:36:17 +02:00
Florent Kermarrec b29a99cd0b liblitedram/sdram.c: Fix DFII_PIX_DATA_BYTES computation.
DFII CSR size is not necessarily multiple of 4 (often the case but not with ECC for example).
2021-07-09 17:32:43 +02:00
George Hilliard 8954041a93 clock/lattice_ecp5/ECP5PLL: Only consider non-dpa clocks as feedback
Dynamically adjusting the phase of a feedback will cause it to unlock.
The phase adjust ports are shared by all the outputs, so there is no
technical way to prevent this.  Allow the user to indicate that they
will not adjust a clock when requesting an output by setting
uses_dpa=False, and only consider those that the user has promised not
to use.
2021-07-08 08:14:14 -05:00
Florent Kermarrec 2b49430f2c README.md: Rewrite Welcome section and update copyright. 2021-07-08 12:08:24 +02:00
Florent Kermarrec 9a51dfb50e tools/litex_sim: Let the SDRAMPHYModel pick default settings. 2021-07-08 09:09:57 +02:00
Florent Kermarrec fced79631e tools/litex_sim: sdram_module_nphases/get_sdram_phy_settings now directly integrated in litedram.phy.model. 2021-07-08 09:01:32 +02:00
George Hilliard 34ba649f38 clock/lattice_ecp5/ECP5PLL: implement 4-output solver
Reimplement the configuration loop to allow all 4 outputs to be used by
the user, if one of them is suitable for use as VCO feedback.

The new strategy is to first iterate over requested outputs to see if
any of them can be used as a feedback source.  If one can, it is
selected, and if no output is suitable, it attempts to instantiate one.
Once the feedback path is selected, the VCO frequency is known and it
attempts to calculate the remaining outputs' settings.

In addition, this implementation now respects datasheet limits in two
new ways:

- It respects the post-input-divider minimum frequency of 10MHz
- It respects the max output frequency of 400MHz for instantiated
  feedback outputs

I am slightly unhappy with the seemingly-repetitive for loops. However
each one has slightly different sematics and I don't see a way to
combine them that doesn't hinder readability.
2021-07-07 01:15:06 -05:00
enjoy-digital dd5413bc9f
Merge pull request #964 from niw/increase_macos_ttyusbmodem_delay
Increase delay for `tty.usbmodem` on macOS.
2021-07-06 18:51:28 +02:00
George Hilliard 8b9f03efba clock/lattice_ecp5/ECP5PLL: Expose standby signal 2021-07-06 08:40:36 -05:00
Yoshimasa Niwa 0953c52eea Increase delay for `tty.usbmodem` on macOS.
**Problems**

On macOS USB CDC ACM, which appears as `/dev/tty.usbmodem*`,
somehow `lxterm` keeps failing to send a payload.

**Solution**

Increase delay.

It's very unknown why to me, however, probably macOS USB CDC ACM
driver implementation issue.

**Testing**

Tested on MacBook Air (2020, M1) for OrangeCrab (rev.0.2) target
with Linux on LiteX SoC bitstream build from current commit and
load prebuild Linux On LiteX image.
2021-07-05 11:46:57 -07:00
Florent Kermarrec f9f1b8e25d liblitedram: Consider 1s window is valid when indirectly seen before 0 (start at 0 and long enough). 2021-06-29 12:03:51 +02:00
enjoy-digital 8192ad335f
Merge pull request #958 from sergachev/master
soc/interconnect/axi: fix valid signal in connect_to_pads for axi lite
2021-06-28 17:37:29 +02:00
Ilia Sergachev 65babd6500 soc/interconnect/axi: fix valid signal in connect_to_pads for axi lite 2021-06-28 11:50:45 +02:00
enjoy-digital 4d959bbc81
Merge pull request #956 from developandplay/simplify-blackparrot-setup
Simplify blackparrot setup
2021-06-28 11:26:50 +02:00
Vadzim Dambrouski 35204225e8 Fix compile error when FST traces are enabled on macOS.
Compile options should be the same for all platforms.
2021-06-27 17:34:43 +03:00
developandplay 9fd9eaea07 Move patch script to python-data 2021-06-27 01:31:05 +02:00
developandplay ac217d818f Set environmental variables in python 2021-06-27 01:07:27 +02:00
developandplay e3f6d8349b Use os methods to expand env vars 2021-06-26 16:30:54 +02:00
developandplay b787ee4411 Move systemverilog files to python-data 2021-06-26 15:45:48 +02:00
developandplay 16b3e08c17 Copy config loader in python 2021-06-26 15:37:17 +02:00