Sebastien Bourdeauducq
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aa8b8da684
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fhdl: allow None statements
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2012-01-15 17:45:54 +01:00 |
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Sebastien Bourdeauducq
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3c7161cc34
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flow: saner endpoint management
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2012-01-15 15:09:44 +01:00 |
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Sebastien Bourdeauducq
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b06e70d849
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corelogic: FSM
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2012-01-09 16:28:48 +01:00 |
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Sebastien Bourdeauducq
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34c69db14a
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endpoint: add _i/_o suffix on signal names
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2012-01-07 21:21:46 +01:00 |
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Sebastien Bourdeauducq
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cdd9977a40
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fhdl: better signal naming heuristic
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2012-01-07 15:30:14 +01:00 |
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Sebastien Bourdeauducq
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b6763c28ea
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constant: equality
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2012-01-07 12:29:47 +01:00 |
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Sebastien Bourdeauducq
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7b395b565e
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verilog: split comb block, use assign statements
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2012-01-07 12:19:06 +01:00 |
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Sebastien Bourdeauducq
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f209bf6b33
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convtools -> tools
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2012-01-07 00:39:28 +01:00 |
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Sebastien Bourdeauducq
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3c1dada9cf
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record: compatibility check
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2012-01-06 23:00:23 +01:00 |
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Sebastien Bourdeauducq
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d7a3bed44c
|
Signal repr
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2012-01-06 11:20:33 +01:00 |
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Sebastien Bourdeauducq
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9366a226bb
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Convert -> convert
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2012-01-05 19:27:33 +01:00 |
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Sebastien Bourdeauducq
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76db20cd9f
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fhdl: encapsulate replicated constants
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2011-12-23 00:35:13 +01:00 |
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Sebastien Bourdeauducq
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8a394f9159
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verilog: comb reset
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2011-12-22 00:04:53 +01:00 |
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Sebastien Bourdeauducq
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4d6be55e9f
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verilog: break down Convert function
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2011-12-21 23:08:50 +01:00 |
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Sebastien Bourdeauducq
|
26e0b817e8
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verilog: ignore variable property in combinatorial block
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2011-12-21 23:00:36 +01:00 |
|
Sebastien Bourdeauducq
|
7456195775
|
Consistent names
|
2011-12-21 22:57:07 +01:00 |
|
Sebastien Bourdeauducq
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4f4d809a4e
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fhdl: better matching of assignment
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2011-12-18 21:49:48 +01:00 |
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Sebastien Bourdeauducq
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dd42b2daff
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fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
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2011-12-18 21:47:29 +01:00 |
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Sebastien Bourdeauducq
|
41e2430e2b
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fhdl: automatic signal name from assignment
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2011-12-18 21:26:51 +01:00 |
|
Sebastien Bourdeauducq
|
d21e095397
|
fhdl: fix series of if/elif/else
|
2011-12-17 20:31:42 +01:00 |
|
Sebastien Bourdeauducq
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6f8a6db40a
|
verilog: get the simulator to run the combinatorial process at the beginning
|
2011-12-17 15:20:22 +01:00 |
|
Sebastien Bourdeauducq
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ec47394012
|
verilog: support for float parameters in instances
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2011-12-17 14:59:27 +01:00 |
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Sebastien Bourdeauducq
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ee6ca729a2
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verilog: user-definable reset and clock
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2011-12-16 22:25:05 +01:00 |
|
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
|
c840848dba
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verilog: use blocking assignment in combinatorial process
|
2011-12-13 14:09:12 +01:00 |
|
Sebastien Bourdeauducq
|
a72faaecdd
|
fhdl: allow a namespace to be specified for Verilog conversion
|
2011-12-13 00:24:40 +01:00 |
|
Sebastien Bourdeauducq
|
eee6980a36
|
fhdl: support Constant parameters for Verilog conversion
|
2011-12-11 20:17:51 +01:00 |
|
Sebastien Bourdeauducq
|
dafef5d744
|
fhdl: fix list references (thanks Lars)
|
2011-12-11 20:17:29 +01:00 |
|
Sebastien Bourdeauducq
|
019ef16db4
|
fhdl: remove broken fragment iadd
|
2011-12-11 01:10:59 +01:00 |
|
Sebastien Bourdeauducq
|
b00581616e
|
convtools: insert reset on variables
|
2011-12-11 01:10:37 +01:00 |
|
Sebastien Bourdeauducq
|
d3127fd5d8
|
autofragment: remove debug
|
2011-12-10 20:48:23 +01:00 |
|
Sebastien Bourdeauducq
|
44f44b8a05
|
fhdl: autofragment
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2011-12-10 20:47:21 +01:00 |
|
Sebastien Bourdeauducq
|
4b15a84505
|
fhdl: fix += for empty fragment
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2011-12-10 20:47:06 +01:00 |
|
Sebastien Bourdeauducq
|
a49ecc4331
|
fhdl: pad support in fragments
|
2011-12-10 20:25:24 +01:00 |
|
Sebastien Bourdeauducq
|
fa63cc1ec8
|
fhdl: replication support
|
2011-12-09 13:11:34 +01:00 |
|
Sebastien Bourdeauducq
|
b0c5b74c22
|
verilog: handle default in case statements
|
2011-12-08 23:04:20 +01:00 |
|
Sebastien Bourdeauducq
|
512655c108
|
fhdl: improve automatic signal naming
|
2011-12-08 21:28:20 +01:00 |
|
Sebastien Bourdeauducq
|
84eb964adc
|
fhdl: support negation operator
|
2011-12-08 21:15:44 +01:00 |
|
Sebastien Bourdeauducq
|
bf021efa2b
|
verilog: fix unary operator conversion
|
2011-12-08 21:15:24 +01:00 |
|
Sebastien Bourdeauducq
|
ed05ec5f6a
|
instances: signal override
|
2011-12-08 18:56:14 +01:00 |
|
Sebastien Bourdeauducq
|
a6b86168ce
|
Simple bus base class
|
2011-12-08 18:47:32 +01:00 |
|
Sebastien Bourdeauducq
|
1b637cea61
|
Instance support
|
2011-12-08 16:35:32 +01:00 |
|
Sebastien Bourdeauducq
|
fab02f84cb
|
fhdl: fix implicit slice index
|
2011-12-07 22:21:30 +01:00 |
|
Sebastien Bourdeauducq
|
82f77180d5
|
fhdl: cleanup value bv
|
2011-12-07 22:21:10 +01:00 |
|
Sebastien Bourdeauducq
|
0e8d894a35
|
Variable conversion
|
2011-12-05 22:00:06 +01:00 |
|
Sebastien Bourdeauducq
|
4340680704
|
Cleanup
|
2011-12-05 19:25:32 +01:00 |
|
Sebastien Bourdeauducq
|
ec51f09c98
|
Case support + register bank generator
|
2011-12-05 17:43:56 +01:00 |
|
Sebastien Bourdeauducq
|
e099f4d52f
|
Reset insertion
|
2011-12-04 22:41:50 +01:00 |
|
Sebastien Bourdeauducq
|
cd8544c758
|
Verilog generator
|
2011-12-04 22:26:32 +01:00 |