77c6cdd78e
cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.
2022-01-25 11:09:15 +01:00
ea6bb3dd80
test/test_clock: Add minimal ECP5Delay test (syntax), rename tests with underscore.
2022-01-25 10:49:33 +01:00
6ff8b6e4ed
Merge pull request #1173 from sergachev/ecp5_delay
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clock/lattice_ecp5: add ECP5 dynamic delay DELAYF primitive support
2022-01-25 10:44:53 +01:00
d059111c92
Merge pull request #1180 from suarezvictor/master
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Add yosys+nextpnr toolchain support
2022-01-24 19:02:02 +01:00
6d7f8888ac
Add yosys+nextpnr toolchain support
2022-01-24 13:35:12 -03:00
6b3eda16f2
Merge pull request #1179 from Technosystem-Labs/vexriscv_hw_breakpoints
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Added Vexriscv hardware breakpoint variants for Mini and Lite.
2022-01-24 08:16:39 +01:00
9e0d8b3f41
Added Vexriscv hardware breakpoint variants for Mini and Lite.
2022-01-24 00:00:26 +01:00
8d3f12ebbd
Merge pull request #1178 from sergachev/gowin_emcu
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Enable LiteX BIOS on Gowin EMCU ARM core
2022-01-23 21:01:06 +01:00
57fef500a7
Merge pull request #1177 from yetifrisstlama/i2c
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bitbang.py: initialize SCL / SDA lines to high on reset
2022-01-23 21:00:20 +01:00
f36619987b
software/bios: update comment
2022-01-23 16:57:33 +01:00
85f892227a
cores/cpu/gowin: re-enable write access to csr bus
2022-01-23 16:34:47 +01:00
e4ceaa7cc2
bitbang.py: initialize SCL / SDA lines to high on reset
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* otherwise might block the I2C bus on reset
2022-01-23 16:11:34 +01:00
0f44723957
cores/cpu/gowin: fix isr table optimization and uart init
2022-01-23 15:37:00 +01:00
d4c12a5231
cores/cpu/gowin_emcu: add software support
2022-01-23 11:20:44 +01:00
3f2a7b9bfd
software/bios: set attribute used on main to fix optimization in some configurations
2022-01-23 11:04:22 +01:00
ef5f6398b2
integration/builder: enable bios on gowin emcu
2022-01-23 11:02:36 +01:00
0e9e57c926
Merge pull request #1176 from Icenowy/gwpsram
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gowin: add hack for copackaged PSRAM
2022-01-23 08:33:29 +01:00
b7b054d48e
gowin: add hack for copackaged PSRAM
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Some Gowin FPGAs has copackaged "PSRAM" instead of "HyperRAM". They're
in fact also HyperRAM, but named differently and because of this needs
slightly changed hack.
Add hack for PSRAM too. In case of two PSRAM chips are used, the bus is
wider so the needed definition is already in place, so the bus width
hack is not needed.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-23 03:08:18 +08:00
44bea44be3
Merge pull request #1172 from stffrdhrn/or1k-marocchino-linux
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Or1k marocchino linux fixes
2022-01-21 19:28:56 +01:00
4b22eda662
clock/lattice_ecp5: add ECP5 dynamic delay DELAYF primitive support
2022-01-21 14:05:28 +01:00
443faef33b
litex_sim: Update SPI Flash support.
2022-01-21 10:05:07 +01:00
bcc9c14c7e
cores/cpu: Fix automatic collection for Rocket/BlackParrot/EOS-S3.
2022-01-20 17:44:35 +01:00
d1746e1286
tools/litex_json2dts_linux.py: Support DTS generator for OpenRISC marocchino
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Marocchino is also a or1k architecture and the DTS file is the same
as mor1kx. I would like to use the dts generator for marocchino too.
This patch introduces a new mapping to derive architecture based on the
cpu_name it then uses the cpu_arch (architecture) to control the DTS
generation rather than the cpu name.
2022-01-20 20:42:15 +09:00
d3942c137d
bios/boot: Support setting EVBAR for Marocchino too
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The Marocchino CPU is an OR1K architecture so it also requires setting
of EVBAR to boot linux.
2022-01-20 20:35:53 +09:00
a76828a40a
soc/add_uart: Fix uart_name="uartbone" case.
2022-01-20 10:23:06 +01:00
928ee285dc
Merge pull request #1171 from enjoy-digital/out-of-tree-cpus
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Simplify CPUs collection and add out-of-tree support.
2022-01-20 09:46:43 +01:00
681f474c66
CHANGEs: Update.
2022-01-20 09:25:49 +01:00
bdc22770e9
cores/cpu: Deprecate external CPU class support (advantageously replaced by out-of-tree support which is more flexible).
2022-01-20 09:25:39 +01:00
c675acb868
cores/cpu: Add out-of-tree CPUs support (By searching CPUs in execution directory).
2022-01-20 09:18:10 +01:00
ba14212129
cores/cpu: Avoid duplication between CPU_GCC_TRIPLE_RISCV64/CPU_GCC_TRIPLE_RISCV32, CPU_GCC_TRIPLE_RISCV32 is just an extension of CPU_GCC_TRIPLE_RISCV64.
2022-01-20 08:49:58 +01:00
576b96ba83
cores/cpu: Switch to automatic CPUs collection.
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Simplify code/maintenance and will also enable out-of-tree CPUs support.
2022-01-20 08:39:22 +01:00
02fe32bd79
tools/litex_server/sim: Deprecate bridge use in favor of crossover (was already supported).
2022-01-19 16:54:56 +01:00
f5e1f1c05b
soc/add_uart: Add list of supported UARTs, reorder and add error message when not supported/found.
2022-01-19 16:40:30 +01:00
3683c5b866
build/sim/platform: Add loose support to request.
2022-01-19 16:39:32 +01:00
11e8a3ce23
soc/add_uart: Simplify/Cleanup.
2022-01-19 16:06:55 +01:00
fda3164be4
soc/add_uart: Separate name/uart_name to allow multiple UARTs in the same design.
2022-01-19 15:48:42 +01:00
6d697f4506
soc/add_etherbone: Improve genericity to allow multiple instances of Etherbone cores.
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ex:
self.submodules.ethphy0 = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks", 0),
pads = self.platform.request("eth", 0))
self.submodules.ethphy1 = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks", 1),
pads = self.platform.request("eth", 1))
self.add_etherbone(name="etherbone0", phy=self.ethphy0, phy_cd="ethphy0_eth")
self.add_etherbone(name="etherbone1", phy=self.ethphy1, phy_cd="ethphy1_eth")
2022-01-19 15:07:55 +01:00
2a17214813
Merge pull request #1169 from sergachev/fix/zynq_software
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Fix Zynq software support
2022-01-19 10:04:48 +01:00
2f433611dd
litex_sim: Add .json support for --rom/ram/sdram-init.
2022-01-19 09:58:38 +01:00
77b2ae14bb
integration/common/get_mem_data: Add proper support for .json.
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- Path is relative in boot.json files.
- Add optional offset (useful when used to initialize a RAM without mapping offset).
2022-01-19 09:38:53 +01:00
6a395fa492
cpu/zynq7000: correct address map
2022-01-19 02:48:13 +01:00
2bc1c3ac99
cpu/zynq7000: enable software compilation
2022-01-19 02:47:18 +01:00
682e4e0b7d
cpu/zynq7000: add boot helper
2022-01-19 02:46:49 +01:00
e9aa747d2b
cpu/vexriscv_smp/args_fill: Fill args in cpu group.
2022-01-18 18:56:02 +01:00
2913f2ecd9
tools/litex_sim: Use new verilator_build_args/argdict.
2022-01-18 18:47:40 +01:00
3d8ffa1897
build/sim/verilator: Add verilator_build_args/argdict to reduce duplication in sim targets.
2022-01-18 18:47:12 +01:00
8289e71ea7
tools/litex_sim: Remove ident_version (now provived by kwargs).
2022-01-18 17:18:50 +01:00
ae70023f0d
soc_core: Switch from --ident-version parameter to --no-ident-version.
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Identifier version is enabled by default and we just need to allow user to easily disable it for determinist builds.
The custom --no-ident-version added to targets can then be avoided with this and this argument will
now be available on all targets.
2022-01-18 14:07:26 +01:00
07c7f664cf
integration/soc/add_sdram: Set default l2_cache_reverse value to False.
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For correct operation of Framebuffer + CPU writes, l2_cache_reverse has to be
set to False on targets. Set it to False by default in LiteX to avoid this.
2022-01-18 11:34:12 +01:00
b958453105
soc/add_video_framebuffer: Use clock_faster_than_sys when equal.
2022-01-17 18:19:23 +01:00
Florent Kermarrec
Victor Suarez Rovere
Mikolaj Sowinski
Ilia Sergachev
Michael Betz
Icenowy Zheng
Stafford Horne