Florent Kermarrec
f4c35e358e
software/bios/sdram: small clean up
2015-03-27 18:24:19 +01:00
Florent Kermarrec
6245dd7b6f
software/bios/sdram: for now desactivate random on address test since it seems to trigger a L2 cache or LASMIcon bug on at least de0nano/minispartan6
...
Memtest sometimes reports 1 or 2 errors with de0nano/minispartan6 on this new test when used with LASMICON. Minicon seems fine. We will have to investigate on this issue.
2015-03-27 16:43:22 +01:00
Florent Kermarrec
f85a4f004b
software/bios/sdram: add random addressing to memtest
...
testing memories with linear access is not good enough. Adding random addressing allow us to detect more eventual issues on our L2 cache or SDRAM controller.
2015-03-27 15:49:16 +01:00
Florent Kermarrec
38d24b637e
software/bios/sdram: make seed_to_data static
2015-03-26 23:05:20 +01:00
Florent Kermarrec
e79a716425
software/bios/sdram: select the type of data we want to generate for memtest with TEST_RANDOM_DATA (debugging hardware is easier with a simple counter)
2015-03-26 22:16:31 +01:00
Florent Kermarrec
9bc71f374a
rename sdram mapping to main_ram
2015-03-21 21:01:46 +01:00
Florent Kermarrec
b75e4b237d
software/bios/memtest: add data bus test (0xAAAAAAAA, 0x55555555) on a small portion of the test zone.
...
we now need to add another random addressing test to avoid linear access on L2 cache
2015-03-21 20:29:15 +01:00
Florent Kermarrec
473997df26
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
2015-03-02 16:52:17 +01:00
Florent Kermarrec
8280acd3a7
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
2015-03-02 12:17:49 +01:00
Florent Kermarrec
0980becb56
sdram: improve memtest by adding 2 different writes/reads
...
doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.
2015-03-02 10:52:22 +01:00
Sebastien Bourdeauducq
36434b62f0
sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE
2014-09-03 15:02:38 +08:00
Sebastien Bourdeauducq
2388bfabc3
bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705.
2014-09-03 14:25:26 +08:00
Sebastien Bourdeauducq
6decb357f1
bios: add sdrrderr
2014-09-01 15:23:37 +08:00
Sebastien Bourdeauducq
57335bdf3f
bios: add DQ filtering to sdrrd, add sdrrdbuf command
2014-09-01 14:58:58 +08:00
Sebastien Bourdeauducq
0ebdf2be6d
bios/sdram: cleanup
2014-08-08 21:57:58 +08:00
Sebastien Bourdeauducq
b61dced909
bios/sdram: set ODT and RESET_N through DFII
2014-08-08 21:57:42 +08:00
Florent Kermarrec
293ac09673
sdramphy/bios: make sdrrd/sdrwr generic
2014-08-08 19:25:10 +08:00
Sebastien Bourdeauducq
dc2024f54d
bios: remove references to 'DDR' SDRAM, as we also support SDR SDRAM
2014-05-23 21:31:26 +02:00
Sebastien Bourdeauducq
1c08aeb21c
Initial mor1kx (OpenRISC) support
...
Based on milkymist-ng-mor1kx by Stefan Kristiansson
2014-05-14 10:24:56 +02:00
Sebastien Bourdeauducq
9e784fc82c
Generate mem.h from SoC description
2014-02-21 17:55:05 +01:00
Sebastien Bourdeauducq
4ba796417d
software: do not attempt to build network/sdram drivers when cores are not present
2013-11-24 23:50:09 +01:00
Sebastien Bourdeauducq
fca0b968e7
generate linker memory map, move all generated files into the same folder
2013-11-24 19:50:17 +01:00
Sebastien Bourdeauducq
26ff6f2a9c
s6ddrphy: style and other minor fixes
2013-07-10 20:39:53 +02:00
Florent Kermarrec
60f1585fef
use Migen s6ddrphy, generate sdram init_sequence in cif.py
2013-07-10 19:56:09 +02:00
Sebastien Bourdeauducq
91d7b656a9
Switch to LASMI, bug pandemonium
2013-06-11 14:18:16 +02:00
Sebastien Bourdeauducq
fdf7f10f54
Automatically build CSR access functions
2013-03-25 14:42:48 +01:00
Sebastien Bourdeauducq
5e6505b946
bios: print number of memory errors
2013-02-24 16:51:03 +01:00
Sebastien Bourdeauducq
dd6eacba62
Remove uses of the RE signal on field registers
2012-10-09 19:08:37 +02:00
Sebastien Bourdeauducq
274a00217e
bios: asmiprobe command
...
Because with reordering architectures come order-dependent intermittent bugs.
2012-08-04 16:32:15 +02:00
