Florent Kermarrec
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261469814f
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add hack to generate verilog with AsyncResetSynchronizer (FIXME)
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2015-01-23 03:18:25 +01:00 |
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Florent Kermarrec
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6003b8af02
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use LiteScope (replace Miscope)
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2015-01-23 01:34:59 +01:00 |
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Florent Kermarrec
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fb7864c2b9
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add missings __init__.py
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2015-01-23 01:14:35 +01:00 |
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Florent Kermarrec
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d45991d6eb
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fix README
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2015-01-23 01:07:51 +01:00 |
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Florent Kermarrec
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ea48f44b90
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add LiteScopeLA example
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2015-01-23 00:46:24 +01:00 |
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Florent Kermarrec
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5c40ff02cb
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add LiteScopeIO example
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2015-01-23 00:15:42 +01:00 |
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Florent Kermarrec
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f35f93a7c5
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start refactoring and change name to LiteScope
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2015-01-23 00:02:53 +01:00 |
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Florent Kermarrec
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7b2135f58f
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add .gitignore
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2015-01-22 21:25:23 +01:00 |
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Florent Kermarrec
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4e3190120e
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fix build with upstream Migen/MiSoC
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2015-01-22 21:23:14 +01:00 |
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Florent Kermarrec
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319a4a7f51
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more doc
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2015-01-22 21:04:36 +01:00 |
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Florent Kermarrec
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b299116ace
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replace SATAX with sata_genx
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2015-01-22 17:15:12 +01:00 |
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Florent Kermarrec
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bbd2a076be
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targets/core: simplify ios generation
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2015-01-22 16:52:26 +01:00 |
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Florent Kermarrec
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8d16a166c4
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change submodules/specials/clock_domains syntax
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2015-01-22 16:04:53 +01:00 |
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Florent Kermarrec
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609f8f9abb
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revert submodules/specials/clock_domains syntax
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2015-01-22 14:00:50 +01:00 |
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Florent Kermarrec
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3346bf8b2b
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frontend: simplify
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2015-01-22 10:45:11 +01:00 |
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Florent Kermarrec
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8638e5dd15
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doc: fix typos
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2015-01-22 09:55:06 +01:00 |
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Florent Kermarrec
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97eb712766
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bist: add random addressing
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2015-01-22 01:56:37 +01:00 |
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Florent Kermarrec
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91bb531641
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bist: add loops parameter for more precision in speed computation
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2015-01-22 01:33:02 +01:00 |
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Florent Kermarrec
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c9761be54f
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command: remove success/failed redundancy (keep failed)
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2015-01-22 00:23:11 +01:00 |
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Florent Kermarrec
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ff0c8e3d22
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add PacketBuffer, simplify architecture and reduce ressource usage
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2015-01-22 00:13:19 +01:00 |
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Florent Kermarrec
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ebf1faed5b
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transport: simplify tx and reduce ressource usage
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2015-01-21 19:11:54 +01:00 |
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Florent Kermarrec
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1b20831541
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transport: simplify and reduce ressource usage
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2015-01-21 18:55:42 +01:00 |
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Florent Kermarrec
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fccf2c9430
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common: clean up
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2015-01-21 12:01:28 +01:00 |
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Florent Kermarrec
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f0f6183c9a
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link/crc: use OrderedDict to generate the same code on each iteration
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2015-01-21 11:48:06 +01:00 |
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Florent Kermarrec
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62bb5b47ca
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doc: fix .PNG extension
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2015-01-21 11:11:01 +01:00 |
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Florent Kermarrec
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5825ec8f47
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command: merge 2 states on tx
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2015-01-21 10:52:56 +01:00 |
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Florent Kermarrec
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d2ce266cba
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fix core generation
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2015-01-21 10:52:18 +01:00 |
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Florent Kermarrec
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0af179f1f2
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doc: add SATA description from Erik Landström's Thesis
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2015-01-21 01:46:30 +01:00 |
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Florent Kermarrec
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c70e8a3853
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change copyright to HKU
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2015-01-20 23:41:33 +01:00 |
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Florent Kermarrec
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578903bc11
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manage reg_d2h errors
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2015-01-20 19:28:56 +01:00 |
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Florent Kermarrec
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d1e2f6d2b0
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bist: show current length in MB
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2015-01-20 15:24:52 +01:00 |
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Florent Kermarrec
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77778d24ae
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bist: add decoding of capabilities
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2015-01-20 15:00:37 +01:00 |
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Florent Kermarrec
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faef2319ad
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bist: decode more infos from identify data
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2015-01-20 12:32:28 +01:00 |
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Florent Kermarrec
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a5ae470ec9
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fix license
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2015-01-20 10:49:37 +01:00 |
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Florent Kermarrec
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0d77c780c6
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copy README chapters to .rst
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2015-01-19 23:28:14 +01:00 |
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Florent Kermarrec
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2bb9c6b649
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add verilog backend to use the core with a "standard" flow
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2015-01-19 20:38:48 +01:00 |
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Florent Kermarrec
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d84ae7c80c
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clean up
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2015-01-19 18:13:43 +01:00 |
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Florent Kermarrec
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18f2933d8b
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add doc skeleton (from emscripten with readthedocs theme)
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2015-01-19 17:10:24 +01:00 |
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Florent Kermarrec
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79dbb6da4b
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replace Makefile with make.py (will enable verilog rtl generation for integration with standard flows)
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2015-01-19 09:45:34 +01:00 |
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Florent Kermarrec
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6de7e15a0c
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refactor code
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2015-01-17 13:22:52 +01:00 |
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Florent Kermarrec
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6f2c7a236c
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add support of identify device command
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2015-01-17 02:35:25 +01:00 |
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Florent Kermarrec
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fadac0cf83
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drivers: fix mask generation when using cond
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2015-01-16 23:50:33 +01:00 |
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Florent Kermarrec
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c227576f3d
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add test_link.py (replace test_bist_mila)
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2015-01-16 21:16:05 +01:00 |
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Florent Kermarrec
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175618bcb4
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use csr_data_width of 32 to speed up data mila upload
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2015-01-16 20:57:01 +01:00 |
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Florent Kermarrec
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083bd54121
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global clean up
- remove initial sims
- remove SATAPHYDeviceCtrl
- rename to LiteSATA
- rename test to bist
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2015-01-16 20:26:15 +01:00 |
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Florent Kermarrec
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e90d97e9c2
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phy: remove GTXE2_COMMON (no longer need since it was a Vivado bug that is now fixed)
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2015-01-16 19:25:35 +01:00 |
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Florent Kermarrec
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d13366dd2d
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bist: use hardware counter for speed calc and remove loops mode
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2015-01-16 18:48:34 +01:00 |
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Florent Kermarrec
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7ccc5f5274
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link/cont: improve timing
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2015-01-16 18:13:07 +01:00 |
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Florent Kermarrec
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1170a1070b
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add need_reset from controller to request system reset when SATA is not locked
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2015-01-15 00:56:47 +01:00 |
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Florent Kermarrec
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8f14f67ea6
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simplify UART2Wishbone and add timeout
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2015-01-14 18:10:37 +01:00 |