Florent Kermarrec
|
cb4be52922
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targets: add Lattice ECP3 versa
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2015-03-17 19:09:43 +01:00 |
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Florent Kermarrec
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70f1f96fda
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litescope/drivers: do not build regs when addrmap is None
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2015-03-17 16:04:31 +01:00 |
|
Florent Kermarrec
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a266deb58e
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LiteXXX cores: fix frequency print in test/test_regs.py
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2015-03-17 16:01:25 +01:00 |
|
Florent Kermarrec
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d2cb41bc63
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LiteXXX cores: convert port parameter to int if is digit in test/make.py
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2015-03-17 15:58:21 +01:00 |
|
Florent Kermarrec
|
2327710387
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liteeth/phy/gmii : set tx_er to 0 only if it exits
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2015-03-17 12:24:06 +01:00 |
|
Florent Kermarrec
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408d0fd2dd
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liteeth: use default programmer in make.py
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2015-03-17 12:12:21 +01:00 |
|
Florent Kermarrec
|
ec6ae75065
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liteeth: use CRG from Migen in base example
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2015-03-17 12:11:51 +01:00 |
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Florent Kermarrec
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a874f85854
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litescope: use CRG from Migen
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2015-03-17 11:52:54 +01:00 |
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Florent Kermarrec
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b2f32ad124
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targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)
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2015-03-17 01:07:44 +01:00 |
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Florent Kermarrec
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faf185d58d
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liteeth: make gmii phy generic
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2015-03-16 23:04:37 +01:00 |
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Florent Kermarrec
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d8b59c03a2
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litesata: avoid hack on kc705 platform with new mibuild toolchain management
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2015-03-14 01:08:36 +01:00 |
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Florent Kermarrec
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28d04ec300
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soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
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2015-03-14 00:49:19 +01:00 |
Sebastien Bourdeauducq
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d09529d483
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targets/simple: use mibuild default clock
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2015-03-14 00:11:59 +01:00 |
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Sebastien Bourdeauducq
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32676fffd2
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soc/sdram: sync with new mibuild toolchain management
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2015-03-13 23:19:08 +01:00 |
|
Florent Kermarrec
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c3c7f627d9
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liteeth/phy: typo (thanks sb)
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2015-03-12 21:54:10 +01:00 |
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Florent Kermarrec
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1b72b81f9c
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targets/simple: use new generic DifferentialInput
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2015-03-12 18:36:04 +01:00 |
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Florent Kermarrec
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f18ae9b9fe
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targets/simple: insert IBUFDS for Xilinx devices (not implemented for others vendors)
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2015-03-12 17:25:01 +01:00 |
|
Florent Kermarrec
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cd6c04b24f
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soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx
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2015-03-12 17:12:56 +01:00 |
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Florent Kermarrec
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767d45727a
|
uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).
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2015-03-12 16:57:38 +01:00 |
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Florent Kermarrec
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b157031e8a
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uart/sim: add pty (optional, to use flterm)
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2015-03-09 23:29:06 +01:00 |
|
Florent Kermarrec
|
6cbf13036b
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liteeth/mac: fix padding limit (+1), netboot OK with sim platform
|
2015-03-09 20:59:34 +01:00 |
|
Florent Kermarrec
|
47cceea222
|
liteeth/mac: use Counter in sram and move some logic outside of fsms
|
2015-03-09 20:22:14 +01:00 |
|
Florent Kermarrec
|
b10836a8eb
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liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit
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2015-03-09 17:21:29 +01:00 |
|
Florent Kermarrec
|
1b58813d13
|
soc: do_exit is now provided by modules
|
2015-03-09 17:18:42 +01:00 |
|
Florent Kermarrec
|
360c849f21
|
liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)
|
2015-03-09 13:23:39 +01:00 |
|
Florent Kermarrec
|
5dbd8af4be
|
liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap
|
2015-03-09 13:23:37 +01:00 |
|
Florent Kermarrec
|
d20b9c2221
|
uart: pass *args, **kwargs to sim phy
|
2015-03-06 12:08:10 +01:00 |
|
Florent Kermarrec
|
af66ca7bad
|
uart: add phy autodetect function
|
2015-03-06 10:19:29 +01:00 |
|
Florent Kermarrec
|
e133777450
|
targets/simple: add MiniSoC
|
2015-03-06 10:10:58 +01:00 |
|
Florent Kermarrec
|
95fa753149
|
liteeth: add phy autodetect function (phy can still be instanciated directly)
|
2015-03-06 10:10:34 +01:00 |
|
Florent Kermarrec
|
bee8ccf6c7
|
soc: enforce cpu_reset_address to 0 when with_rom is True
|
2015-03-06 08:21:16 +01:00 |
|
Florent Kermarrec
|
2b9397ff5b
|
targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
|
2015-03-06 07:56:45 +01:00 |
|
Florent Kermarrec
|
52f1c45407
|
LiteXXX cores: fix test_reg.py
|
2015-03-04 23:13:14 +01:00 |
|
Sebastien Bourdeauducq
|
60e87f6e87
|
Merge branch 'master' of https://github.com/m-labs/misoc
|
2015-03-04 00:46:41 +00:00 |
|
Sebastien Bourdeauducq
|
073641faa1
|
litesata: fix permissions and imports
|
2015-03-04 00:46:24 +00:00 |
|
Florent Kermarrec
|
200791c81d
|
uart: generate ack for rx (serialboot OK with sim)
|
2015-03-04 00:57:37 +01:00 |
|
Florent Kermarrec
|
7c058a52c9
|
com/spi: use .format in tb
|
2015-03-03 10:44:05 +01:00 |
|
Florent Kermarrec
|
0716dadaf2
|
targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works
|
2015-03-03 10:39:31 +01:00 |
|
Florent Kermarrec
|
1d4dc45436
|
LiteXXX cores: use format in prints
|
2015-03-03 10:29:28 +01:00 |
|
Florent Kermarrec
|
f27e7a4b22
|
litesata: remove unneeded clock constraint
|
2015-03-03 10:24:05 +01:00 |
|
Florent Kermarrec
|
0bcd6daf63
|
soc: remove is_sim function
|
2015-03-03 10:15:11 +01:00 |
|
Florent Kermarrec
|
905be50451
|
sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy
|
2015-03-03 09:55:25 +01:00 |
|
Florent Kermarrec
|
9210272356
|
sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence
|
2015-03-03 09:23:21 +01:00 |
|
Florent Kermarrec
|
2f7206b386
|
sdram: revert use of scalar values for DFIInjector
|
2015-03-03 09:09:54 +01:00 |
|
Florent Kermarrec
|
9df60bf98e
|
lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)
|
2015-03-03 09:02:53 +01:00 |
|
Sebastien Bourdeauducq
|
ff29c86fe1
|
litesata/kc705: use FMC pin names
|
2015-03-03 01:02:50 +00:00 |
|
Sebastien Bourdeauducq
|
8e48502d03
|
spiflash: style
|
2015-03-03 00:54:30 +00:00 |
|
Sebastien Bourdeauducq
|
2513833a24
|
README: 80 columns
|
2015-03-03 00:17:34 +00:00 |
|
Sebastien Bourdeauducq
|
69a0c597ad
|
make.py: use ternary getattr
|
2015-03-02 23:54:00 +00:00 |
|
Florent Kermarrec
|
410a162841
|
sdram: disable by default bandwidth_measurement on lasmicon
|
2015-03-02 19:53:16 +01:00 |